General questions, their answers, and tips for ECEn 220.

Default net type: Verilog will default your signals to a 1 bit wire if you don't declare them as anything. This can mess you up when you have typos! To prevent this from happening, put `default_nettype none at the top of all your Verilog files. Synthesizing or Simulation your code will then throw errors when any undeclared names are encountered. ¹⁾ Note that if you use this, you'll have to assign types to all your inputs and outputs. Usually, you'll be fine just setting this to wire, like the following:

input wire A;

Drawing Truth Tables: When drawing a truth table, fill out the binary inputs by writing in columns first rather than rows. Alternate between 0s and 1s in every row down the right-most column, then every 2 rows in the second to right-most column, then every 4 rows, then every 8, etc.

Q: Are Structural, Dataflow, and Behavioral Verilog all separate languages?
A: No, they are all just Verilog. They can all be used together. However, they are different approaches to hardware design. Each has its usefulness in a given situation.
In this class, the three are split apart to gradually introduce you to the power of Verilog. They are also split apart to match the class's curriculum pace.

Stuck in a Lab: if you get to a point in a lab where you have no idea what its talking about, make sure that you have read all the previously listed tutorials in the lab! Sometimes you may need to reread past labs' tutorials. You can easily view all the tutorials on the Tutorials page.

Nexys 4 clock speed: 100 MHz

Assigning a thinner signal to a wider signal: What happens if I assign a k-bit signal to a k+n bit signal? In this case:

logic [7:0] signalA;
assign signalA = 1'b1;

signalA will be updated to 00000001. In general, the lower bit wide signal gets left padded out with zeros to the size of the wider signal.

Possible solutions:

• Click on Simulation Settings. If Generate scripts only is checked, uncheck it. Having this checked will stop the simulation from being executed.
• Close all other simulation tabs that are open. If they say something like the simulation can't be closed then you'll have to go into each tab and manually close that simulation then close the entire tab.