This page contains an index to all of the tutorials in each of the labs. You will likely need to refer to these tutorials more than once as you complete the labs in the class.

• Instructions for Completing ECEN 220 Laboratory Assignments
• Creating a CAEDM Account
• Using CAEDM Storage (J Drive)
• Printing to a CAEDM Printer
• Using the CAEDM Scanner
• Setting Jumpers on the NEXYS 4 Board
• Downloading a bit file to the Nexys 4 Board
• Digital Lab Overview (video)
• NEXYS 4 FPGA Board Overview (video)
• Selecting the Display Video Input

• 7400 Series Logic Devices
• Building Logic Circuits on a Breadboard

• ECEN 220 SystemVerilog Coding Requirements
• Creating a new Vivado Project
• Adding a SystemVerilog design module to a project
• Viewing SystemVerilog as a Schematic
• Starting the Vivado HDL Simulation Tool
• TCL Tutorial 1
• Using Constraint Files (XDC)
• Adding a Constraints File to your Project
• Running the HDL Synthesis Tool
• Running the Implementation Design Step
• Running the bitgen Design Step

• Managing Hierarchy in Vivado
• Adding a Testbench and Simulating with a Testbench
• TCL Tutorial 2

• Generating and Downloading a Bitstream File Using Vivado
• Using TCL Files in Simulations
• Adding Waveforms to Your Simulation
• Using the Oscilloscope
• Installing Putty on a Personal Machine