As with all software, Vivado has a number of “features” which you will sometimes have to deal with. This page is to help with a number of commonly encountered issues you may need to understand.

Before implementing anything in this section remember that anytime you make a change to your verilog code the simulation needs to be rerun. Your code describes your circuit and if you change it you change the circuit you are simulating.

It sounds cliche, but it often works. Sometimes relaunching the simulation isn't sufficient and the old simulation needs to be closed by exiting out of the simulator completely.

1. Exit out of Vivado.
2. Open your file explorer and navigate to your project (It should be in your J-Drive).
3. There will be several files including a .xpr file, which is your actual project, and a .srcs file, which has all of your source code. Your .xpr and .srcs files are very important. Do NOT delete them! The rest of them however, are created every time you open your project in Vivado and run a simulation. Deleting these files will 'clear your cache' and get rid of any 'gunk' in your simulator that might be preventing new simulations from being started or running correctly.
4. Now reopen Vivado and open your project, or open your .xpr file and it will automatically be opened in Vivado.

Run the following command in the tcl console:

   set_property INCREMENTAL true [get_filesets sim_1]

OR do the following steps:

1. In Vivado, right click on Simulate and select Simulation settings.
2. On the right side there is an 'Advanced' tab. Open it.
3. Check the first box where it says, “Enable Incremental Compilation”
4. Exit out of your simulation if you haven't already and reopen it. If this doesn't work you may need to restart Vivado after making the change.