The purpose of this tutorial is to guide you through the steps for creating a new project in the Vivado design suite for developing logic circuits for the NEXYS4 FPGA board.

Follow these steps to create a project:

1. Open Vivado. There should be a shortcut for it on the desktop.
   
2. Click create new project. Click next.
3. Name your project after the lab that its for.
4. Check the Create project subdirectory box.
5. Type in a loaction path or click … to select a destination folder.
6. Select your labs folder in the J: drive. Click next.
7. Select the RTL Project button and check the do not specify sources at this time box. Click next.
8. Find the correct part by selecting the following filter information or by searching for the part name directly. If you do not select the correct board, you will have many problems.
   • Family: Artix-7
   • Package: csg324
   • Speed grade: -1
   • Part Name: xc7a100tcsg324-1
     
9. Click next, then finish!

For future reference, the part name xc7a100tcsg324-1 is also located in the sidebar and links to this tutorial.

After you have created your project, you should copy and paste the following commands and run them in the Tcl Console. You don't have to run them one at a time; you can copy the full set of commands, paste them in the Tcl Console and press Enter to run all of them. EACH TIME YOU CREATE A NEW PROJECT, YOU SHOULD PASTE AND RUN THESE COMMANDS.

set_msg_config -new_severity "ERROR" -id "Synth 8-87"
set_msg_config -new_severity "ERROR" -id "Synth 8-327"
set_msg_config -new_severity "ERROR" -id "Synth 8-3352"
set_msg_config -new_severity "ERROR" -id "Synth 8-5559"
set_msg_config -new_severity "ERROR" -id "Timing 38-313"
set_msg_config -new_severity "ERROR" -id "Timing 38-282"

You can also create an empty project directly by running a TCL command without using the GUI. The following command demonstrates this with the part used on the NEXYS 4 board:

create_project <project name> <Path of project> -part xc7a100tcsg324-1

This is an example of creating a new project in a specific directory on the J: drive.

create_project proj J:\ee220\labs\StructuralVerilog\proj -part xc7a100tcsg324-1

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