This page contains the detailed scripts of the videos used in the tutorials.

Summary: with an empty project, you are ready to add your design file.

• There are several ways to add a file. Summarize each of the video.
• Go through the check boxes for adding the file (various windows and what they do)
  • Use a file that is not the lab solution but something similar. Put a known syntax error in the file so it shows up as an error.
• TCL command for adding a file:
  • add_files -norecurse C:/wirthlin/ee220/git/labs/StructuralVerilog/solution/TestFunction.v
  • update_compile_order -fileset sources_1
  • update_compile_order -fileset sim_1
  • update_compile_order -fileset sources_1
  • update_compile_order -fileset sim_1
• Go through the syntax error process of this file
  • Highlight the syntax error
  • Show them the error reporting so they can find the errors
  • Double click the file so they can edit and fix the file
  • FIx the file and show the syntax error gone

• Follow the existing tutorial pretty closely
• Add a discussion on missing ports and how to fix them

• Discuss the purpose of the simulation tool. Emphasize its importance. You will spend most of your time in this tool - get to konw it well. The better you understand how to use this tool, the easier it will be fior you to complete these labs.
• Discuss how to open the tool (can't open it unless all of the syntax errors are gone). May see other (elaboration) errors that did not show up in the analysis tool. Need to fix these before proceeding. Show how to open the tool.
• Give an overview of the simulation IDE
  • Scopes
  • Objects
  • Waveform
• Running a simulation
  • Press the run for time button
  • Type “run 10 ns” command
  • Discuss what they are seeing (what is hte blue and what is the red)
• Setting values for inputs
  • Do this using window and also with TCL command
  • Show this
• Writing TCL scripts
  • Give an example script that they can copy and paste
• Show the zooming and zoom out of the tool