If you need to see a waveform in the simulation window but it hasn't been added automatically, you can use the add_wave command. Vivado's simulation tools automatically add the inputs, outputs, and wires of the module being simulated but it does not add any inner ports or wires from sub-modules. This is solved by using add_save.

Use this command in a TCL file or in the TCL console.

Below are some examples of how to use the command, along with the Verilog for the modules they're accessing.

Here is the Verilog. myTopModule is the module that is being simulated, thus the inner wires of the sub module will not be shown automatically in the simulation.

// this is the sub module that is contained within the top module
module sub(anInputPort, anotherInputPort, anOutputPort);
  input aPort;
  output anotherPort;
  wire myInnerWireName, anotherInnerWireName;
  // arbitrary operations simply for example purposes
  assign myInnerWireName = ~aPort;
  assign anotherInnerWireName = anotherInputPort ^ myInnerWireName;
  assign anOutputPort = myInnerWireName & anotherInnerWireName;
 
endmodule
 
// this is the module that is being simulated
module myTopModule(A, B);
  input A, B;
  output C;
  // the sub module
  sub innerModuleName(A, B, C);
 
endmodule

Here are the TCL commands to add the waves inside of the sub module so that you can see them in the simluation.

  # you can add wires
  add_wave innerModuleName/myInnerWireName
  # and you can add ports
  add_wave innerModuleName/anInputPort
 
  # with options
  add_wave innerModuleName/myInnerWireName -radix bin
  add_wave innerModuleName/myInnerWireName -name waveNameForSimulation
  add_wave innerModuleName/myInnerWireName -radix bin -name aDifferentWaveformName

• add_wave myModule/mySubModule/portName will add the port portName from inside mySubModule which is inside myModule. mySubModule and myModule must be the instance names of the modules.
• -radix bin is used to change the radix of the waveform when its displayed on the simulation. In this case, the radix is being set to binary. See the table below for other options.
• -name waveNameForSimulation is used to give the waveform a name in the simulation. This doesn't have to correspond to anything in your code and is totally arbitrary, though some of the labs ask that you give specific names to ports.
• You can use -radix and -name at the same time, along with any other options.

Useful values for -radix are listed below.