This will show you how to add a new SystemVerilog source file to an existing project. You should make a new source file for every individual SystemVerilog module you make.

1. First, click Add Sources. This button is located in multiple places. (See video above)
2. This will open the New Source Wizard. Click Add or create design sources then next.
3. Click Create File.
   Change the File Type to SystemVerilog and choose where you want to save the new file. Enter a name for the file and click OK.
   You can add more files before going to the next step if you want, but you can also do so any time later. Click Finish if when you're done adding files.
4. Now you can enter all the port information for each module you're adding. You can type it all in the prompt they give you, or just click OK (and then Yes if you didn't modify anything) to type it in yourself in the SystemVerilog file. When you're done, click OK.
5. Now your new source(s) will be available in the sources pane under Design Sources. (They will also be visible under Simulation Sources.) To edit one of your sources, find the file in the sources pane and double click it to open it.

Make sure you save your SystemVerilog file often, especially before running a simulation or generating a bitstream file.

This probably won't be useful in early labs but will be necessary in the later ones. This steps you through adding a source file that you have previously made (either in a past lab, or downloaded from the course website).

1. Go through steps 1 and 2 in the section above.
2. Instead of clicking Create File, click Add Files.
3. Browse to the location of the source file you wish to add.
   1. If you created the source in Vivado, and saved the file internal to the project, you'll have to navigate to that project's folder, then to the subfolder named <project name>.srcs then sources_1 then new.
4. Make sure the “Copy sources into project” checkbox is marked.
5. Click Finish.

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