User Tools
Table of Contents
Common TCL Commands
This page provides a brief summary of common TCL commands that may help you during your laboratory assignments.
| Project Management | |
|---|---|
| Command | Description |
| create_project | Create new Vivado Project |
Project Management
Creating a new project
create_project <project name> <Path of project> -part xc7a100tcsg324-1
Adding a Verilog file to the project
add_files -norecurse C:/wirthlin/ee220/git/labs/StructuralVerilog/solution/TestFunction.v update_compile_order -fileset sources_1
Adding a constraints file (.xdc) to the project
add_files -fileset constrs_1 -norecurse <filename.xdc>
Simulation
Start the simulation
launch_simulation
Exit the simulation
close_sim
Restart the simulation
This restarts the simulation at time t=0 without exiting the simulation. You may want to run this command if you want to start the simulation over without relaunching the simulation tool.
restart
Run the simulation
run 10 ns
Force a value on a signal
add_force <signal_name> <value>
RTL Analysis
Generate schematic of RTL design:
synth_design -rtl -name rtl_1
Close schematic of RTL design:
close_design
