Common Warnings and Errors
This page provides a summary of common warnings and errors that you may encounter while completing the labs. If you do not see a warning here then let a TA know so we can add your error to the lsit.
Simulation
| Warning | Description | Possible Resolution |
| Module <module name> has a timescale but at least one module in design doesn't have timescale. | A verilog file does not have a timescale but another higher-level module does. | This warning can be ignored but if you want the warning to go away, add a timescale line to your Verilog. |
Synthesis
| Warning | Description | Possible Resolution |
| <signal name> is not declared | You are using a signal that has not been declared. | Declare the signal. This could also be a typo - if you are using a signal that has been declared but have mistyped the signal name you may also get this error. |
| Net <net name> in <module name> does not have driver. | The net in your design isn't driven by anything. | This is often due to a misspelling or forgetting to drive the signal with a value. |
| design <design name> has unconnected port <port name> | The port is not hooked up inside of the design anyware | This could be due to a misspelling or just not hooking up the port to anything. This must be resolved with all ports. |
| multi-driven net <net name> | Indicates that there is a net in your design that is driven in more than one place. | Go back to your code and find all locations when this net is assigned. Modify your code so that it is assigned in only one place. |
| design <design name> has port <port name> driven by constant | Indicates that after logic minimization an output port is reduced to a constant '0' or '1' | This may or may not be a problem. You should review your code to see if this signal really should be a constant. |
Implementation
| Warning | Description | Possible Resolution |
| There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. | Indicates that you did not add timing constraints to your .xdc file. This is ok if you do not have a clock. If you have a clock, you need to add a clock timing constraint. | |
| No user defined clocks were found in the design! | Indicates there is no clock in the design. This is ok if you don't have a clock. If you have a clock, you need to define one in your .xdc file. | |
| [DRC 23-20] Rule violation (PLIO-7) Placement Constraints Check for IO constraints - An IO Bus sw[15:0] with more than one IO standard is found. Components associated with this bus are: LVCMOS18 (sw[9], sw[8]); LVCMOS33 (sw[15], sw[14], sw[13], sw[12], sw[11], sw[10], sw[7], sw[6], sw[5], sw[4], sw[3], sw[2], sw[1], sw[0]); | This warning is telling you that the I/O standard (voltage in this case) is not the same for all switches. sw[8] and sw[9] are 1.8 volts and all of the others are 3.3V. This is how the board was designed and we have no control of these settings. You can safetly ignore this message. | |
| Error | Description | Possible Resolution |
Bitstream Generation
| Error | Description | Possible Resolution |
| [DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 8 out of 27 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. . . . | This is due to the fact that some of the top-level I/O signals do not have .xdc constraints. | Create a I/O placement constraint for every top-level I/O signal |
