There are many different styles of SystemVerilog code that you can use to generate combinational circuits.

Consider the following logic function that outputs a 1 when an odd number of the three input bits are 1. (This is a 3-input XOR).

logic [3:0] in;
logic       out;
 
<Combinational Logic Here>

Assuming the above SystemVerilog code, there are many different ways to implement the combinational logic:

Sum of Products:

logic not0, not1, not2;
 
not(not0, in[0]);
not(not1, in[1]);
not(not2, in[2]);
 
and(term1, not2, not1, in[0]);
and(term1, not2, in[1], not0);
and(term1, in[2], not1, not0);
and(term1, in[2], in[1], in[0]);
or(out, term1, term2, term3, term4)

Minimized (single XOR gate):

xor(out, in[2], in[1], in[0]);

Using assign statement, and the ternary operator:

assign out = in[2] ? (in[1] ? (in[0] ? 1'b1 : 1'b0)
                            : (in[0] ? 1'b0 : 1'b1))
                   : (in[1] ? (in[0] ? 1'b0 : 1'b1)
                            : (in[0] ? 1'b1 : 1'b0));                                                                               

Using assign statement, with sum of products, and dataflow operators :

assign out = (~in[2] & ~in[1] & in[0]) | (~in[2] & in[1] & ~in[0]) |
             (in[2] & ~in[1] & ~in[0]) | (in[2] & in[2] & in[0]);

Using assign statement, vectored comparison operators, binary literals:

assign out = (in == 3'b001) || (in == 3'b010) || (in == 3'b100) || (in == 3'b111);

Using assign statement, vectored comparison operators, decimal literals:

assign out = (in == 3'd1) || (in == 3'd2) || (in == 3'd4) || (in == 3'd7);