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Combinational Logic Styles
There are many different styles of SystemVerilog code that you can use to generate combinational circuits.
Consider the following logic function that outputs a 1 when an odd number of the three input bits are 1. (This is a 3-input XOR).
| in[2] | in[1] | in[0] | out |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 |
