In this lab you will create a digital stopwatch. As shown in the video below, the stopwatch will be displayed on the eight-digit seven-segment display.

• Digits 7:6 will display minutes, digits 5:4 will display seconds, and digits 3:0 will display ten-thousandths of a second.
• Switch 0 will start and stop the timer.
• Button CPU_RESET will reset the timer.

• Create a sequential circuit using multiple counters.
• Practice with SystemVerilog hierarchy and parameters.

Read about the Seven Segment Controller module that is provided to you. The module cycles through the eight seven-segment digits, lighting up one at a time.

• Why doesn't the Seven Segment Controller just display all eight digits at the same time?
• How long (in microseconds) is each digit illuminated for?

At the heart of your stopwatch will be a counter module for each of the eight digits. The counter should be a modulus counter, meaning it counts up to some predetermined value, then rolls over to 0 and continues counting.

You will use a SystemVerilog parameter, MOD_VALUE to indicate the modulus value. The counter should reach (MOD_VALUE-1) and then roll over to 0. This approach will allow us to use this module for digits that count 0-9, as well as digits that count 0-5. Consult the Parameterization in Dataflow SystemVerilog section in the textbook for an example on adding parameters to your SystemVerilog modules.

What you need to do:

• Create a Vivado project.
• Write the SystemVerilog for the mod_counter module.
• Create a tcl simulation script, and verify that your counter is working. Make sure your simulation is thorough; for example, check that the counter only counts when increment is high, and that the rolling_over output is high only in the appropriate condition.

Include you Tcl simulation script in your lab report.

Pass-Off: Show the TA your simulation and explain how you tested the correctness of your module.

In this exercise you will create the stopwatch module which will consist of eight instances of your mod_counter module. Each of these instances will be responsible for generating the value for one digit of the display.

Each rolling_over output is fed into the increment signal for the next most significant digit, as shown below. A counter is added to the module that rolls over every 0.0001s. When this counter rolls over, it should generate a single cycle pulse that is input to the increment signal for the least significant digit.

The 0.0001s counter should increment every cycle that the run input is high, and reset to 0 if the reset input is high.

Make sure you set the roll-over parameter for each of your mod_counter instances. The most significant two digits represent minutes, and the next two digits represent seconds; both should roll over at 59. The lower four digits represent fractions of a second, and should behave accordingly.

Given that the system clock is 100MHz, what value does your counter need to count to in order to roll over every 0.0001s?

Create a tcl simulation script to simulate the behavior of your stopwatch module. You will likely need to simulate for several milliseconds to check that the lower digits are functioning correctly. It will take too long to simulate the upper digits, so you will have to wait until next exercise to test it on the board. In your simulation, make sure to check that:

• The digitX outputs increment appropriately.
• Your least significant digit increments every 0.0001s.
• The stopwatch only runs when the run input is high.
• The digits roll over correctly.

Include your Tcl simulation script in your lab report.

Pass-Off: Show the TA your simulation and explain how you tested the correctness of your module.

In this exercise you will create the top-level module and test your stopwatch on the board.

Create the top-level module as follows:

Your top module should:

• Instantiate both your stopwatch module, as well as a SevenSegmentControl module.
• Connect your digit values output from the stopwatch module to the dataIn input of the SevenSegmentControl.
• Turn on the appropriate decimal point.
• Note: The CPU_RESETN button is active-low. This means it behaves differently than the other buttons you have used: it is a 0 when pressed and a 1 otherwise. You will need to invert the signal when connecting it to your stopwatch and SevenSegmentControl modules.

Be sure to include an appropriate constraints file:

• Note: For this lab, and all subsequent labs that use the clk pin, you should also include the line from the constraints file immediately below the clk pin contraint (create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}];). This informs Vivado that the clock runs at 100MHz.

Pass-off: Show the TAs your stopwatch working on the board.

Submit your SystemVerilog modules using the code submission on Learning Suite. (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards).

Here are some ideas for personal exploration in this laboratory:

• Use additional switches to make your stopwatch run faster or slower than real-time.
• In the first exercise, is the rolling_over output a mealy or moore-type output? Would the stopwatch work if the other type were used? What might be the advantages/disadvantages?
• Modify your design to work as a countdown timer when sw1 is high, and a count-up timer when sw0 is low.