The purpose of this lab is to create a circuit to drive a custom color on a tri-colored LED using “Pulse Width Modulation”.

• Create a sequential circuit using behavioral SystemVerilog
• Create a pulse-width modulated (PWM) controller
• Learn to control a tri-colored LED using three PWM controllers
• Learn how to use an oscilliscope to measure the width of PWM controllers

In several of the previous laboratories you used the 16 green colored LEDs that are located just above the switches. The circuits you created in previous labs used the LEDs in either the “on” or “off” state by driving the LED with a constant logic value of '1' or a logic '0'. For this lab, you will create a circuit that is able to vary the intensity of the LED so you can control its brightness anywhere between the “off” state and the fully “on” state.

Providing a variable intensity for the LED can be done with a technique called “Pulse Width Modulation” or PWM. A pulse width modulated signal is a signal that toggles between '0' and '1' and varies the ratio of '1' on time and '0' off time. When attached to an LED, the intensity of the LED can be increased by increasing the amount of time the signal is set to a '1' and the intensity can be decreased by decreasing the amount of time the signals is set to '1'. The waveforms shown below demonstrate three pulse width modulated signals. The first signal has a 90% duty cycle or a PWM signal in which the signal is '1' 90% of the time. The second signal is a 50% duty cycle signal and the third is a 10% duty cycle.

Consider a pulse width modulated circuit that operates with a repeating period of 2¹⁴ clock cycles operating with a 100 MHz clock.

How many clock cycles will this pulse be high for a pulse with a duty cycle in each of the following situations: A) 90% Duty Cycle, B) 50% Duty Cycle, and C) 10% Duty Cycle.

In this exercise, you will create a reusable Pulse Width Modulation (PWM) module that will provide a PWM signal based on an input signal that indicates the width of the modulated pulse. You will use three of these modules in the top-level design to adjust the intensity of three colors in a tri-colored LED. Begin this exercise by creating a SystemVerilog module with the following name and ports.

Begin your module by creating a sequential counter using behavioral SystemVerilog. This counter should continuously increment by one during each clock cycle. Note that you will need to reset the counter to zero to be able to simulate your module.

Section 17.5 of the textbook mentions some of the reset problems with registers. While you could add a 'reset' input to your module and reset your counters at the start of your simulation, this code will accomplish the same goal:

logic[13:0] counter = 0;

always_ff @(posedge clk)
   counter <= counter + 1;

Note that this only initializes our counter because the always_ff block interprets it as a series of flip-flops. If we tried this with inputs or with other wires then Vivado would give us an error.

Determine how long it takes for your 14-bit counter to count a full sequence from 14'h0000 to 14'h3fff using the 100 MHz clock on the FPGA board.

After building the counter, create the output forming logic associated with the pulse-width modulation output signal. This output forming logic will generate a pulse that has the value of '1' for “width” clock cycles. This is done by generating a '1' signal when the counter value is less than the “width” input. Otherwise this logic should generate a '0'. A flip-flop should be added to the output of his combinational output signal to remove glitches in the pulse-width modulated signal as shown in the figure below.

After creating your pulse width modulation module, simulate your module with a TCL script to validate its basic functionality. Your TCL script should include the following:

1. Specify a 100 MHz repeating clock signal
2. Set a value for “width”
3. Run through a full pulse sequence (and then manually measure the width)
4. Set a different “width”
5. Run through a full pulse sequence (and then manually measure this width)

Include a copy of your .tcl script in your report.

After simulating your module with a .tcl script, verify that your module works by simulating the following testbench file.

tb_pwm.v

Provide a copy of your SystemVerilog PWM module in your lab report.

Exercise 1 Pass-off: Show a TA your pwm module, your tcl file, and your testbench output.

In the top-level module you are going to create a circuit that controls a “Tri-colored LED”. As the name implies, a tri-colored LED is a single LED package that has three different colored LEDs within the package: Red, Green, and Blue. By carefully controlling this LED, you can mix different intensities of these three colors to generate any arbitrary color. Your top-level circuit will need to drive the Red, Green, and Blue inputs of this LED. You will use one PWM module for each color to adjust the color intensities. Be aware that a 100% duty cycle causes the LEDs to be uncomfortably bright, so we will limit our range from 0% to 50%.

A schematic of the circuit that drives the tri-colored LED is shown below.

Begin the top-level design by creating a SystemVerilog module with the following ports:

After creating your top-level module and ports, instance three copies of the PWM controller you created in the previous exercise. You will have one PWM controller for each of the three colors of the tri-colored LED.

Follow these guidelines when hooking up your PWM controllers:

• Attach the top-level clk input to the clk input of each module.
• Attach the pulse output of the controller to the appropriate top-level output port: pulse_red, pulse_green, and pulse_blue.
• The “width” input of each PWM controller must be 14 bits. The actual width of each controller will be set by the user using the toggle switches. The 14-bit width signal for each controller should be set as follows : bits[12:9] of the width signal are tied to appropriate switches (described below) and bit[13] and bits[8:0] are tied to zero. The switches used for each color are described below:
  • sw[3:0] - blue pulse width
  • sw[7:4] - green pulse width
  • sw[11:8] - red pulse width

By connecting our switches to bits[12:9] we are controlling how long the LEDs will turn on each cycle. If our switches are set at 0000 then the width will be 14'h0000 and the count will never be less than that. If our switches are 1111 then the width will be 14'h1E00 and the count will be less than that for approximately half of the cycle.

How many different colors can you generate with this configuration?

In addition to the three PWM controllers, you should add the seven-segment display controller to your top-level design so you can view the pulse settings of each color. Hook up your display controller as follows:

• Only enable digits 0,1, and 2 (disable the other five digits)
• Do not turn on any of the digit points
• Assign the value for digits 0, 1, and 2 as follows:
  • Digit 0: Blue intensity (sw[3:0])
  • Digit 1: Green intensity (sw[7:4])
  • Digit 2: Red intensity (sw[11:8])

Debug Pins

In this lab you will be looking at the PWM output signals with a logic analyzer. In order to view these signals, we need to route them to pins on the FPGA that are easily accessible. To do this, we assign debug[2:0] to our PWM signals, essentially renaming them, so that in our XDC file we can connect them to the pins JA[1], JA[2], and JA[3]. Simply connect debug to the PWM signals in this step, you will add the constraints in Exercise 3.

• debug[0] - Red PWM signal (JA[1])
• debug[1] - Green PWM signal (JA[2])
• debug[2] - Blue PWM signal (JA[3])

After completing your top-level module, simulate to make sure that it operates correctly. Create a TCL script to simulate your module and make sure your script sets at least three different input values of the switches to display three different colors. Make sure the PWM waveforms complete at least one full cycle for each of the three examples.

Provide a copy of your top-level simulation TCL script.

Provide a copy of your top-level SystemVerilog file.

Exercise 2 Pass-off: Show a TA your top-level module and your simulation.

Before synthesizing your design, you will need to create an .xdc file that contains the pin locations of each port in your design. Most of the pins used in this design are the same as pins used in previous designs (buttons, switches, seven-segment display, etc.). However, you will be using several new FPGA pins to connect to the LEDs and the debug port. The new I/O pins you will use include the following:

• LED16 (tri-color LED)
• JA connector port (for debug signals)

The following example code demonstrates how these I/O pins can be attached to your top-level FPGA pins:

set_property -dict { PACKAGE_PIN R12   IOSTANDARD LVCMOS33 } [get_ports { pulse_blue }]; #IO_L5P_T0_D06_14 Sch=led16_b
set_property -dict { PACKAGE_PIN M16   IOSTANDARD LVCMOS33 } [get_ports { pulse_green }]; #IO_L10P_T1_D14_14 Sch=led16_g
set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { pulse_red }]; #IO_L11P_T1_SRCC_14 Sch=led16_r

set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { debug[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { debug[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { debug[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]

After completing your .xdc file, proceed with the synthesis of your design.

Provide a summary of your synthesis warnings.

After successfully synthesizing your design, proceed with the implementation and bitstream generation of your design. Once the bitstream has been generated, download your bitstream to verify that it works correctly.

Indicate the number of Look-up Tables (LUT) and Input/Output (I/O) pins for your design.

Exercise 3 Pass-off: No pass-off for this exercise.

For this final exercise, you will learn how to use the logic analyzer to view the PWM signals generated by your circuit. A logic analyzer is an important piece of test and measurement used to debug digital systems by providing visibility into the actual operation of system signals on your device.

Before proceeding with this exercise, complete the Using the Oscilloscope tutorial. Make sure you use the logic analyzer instead of the analog probes.

After completing the tutorial, hook up the logic analyzer to your three PWM signals. The JA ports can be found here on the NEXYS4 board:

As described above, your PWM signals should correspond to the following JA ports:

Once you have connected the logic analyzer to your board, download your bitfile onto the board and measure the PWM signals with different pulse widths. Once you have the logic analyzer successfully capturing your signals, set the 12 switches to the value 0x36C. Using this setting, complete the following:

Indicate the measured signal width of the Red, Green, and Blue signals

To pass off this laboratory, demonstrate to the TA the following:

• Pass offs for Exercise 1 and 2
• Your working PWM circuit
• The logic analyzer displaying the real-time waveforms of your PWM circuit

How many hours did you work on the lab?

Please provide any suggestions for improving this lab in the future.

Here are some ideas for personal exploration in this laboratory:

• Experiment with different colors using the switches and see how many different colors you can distinctly identify.
• Learn more about Tri-Colored LEDs online.
• Learn a new simulation technique or feature.
• Experiment with a different pulse generator that uses a different number of bits than specified in the lab.
• Increase the maximum duty cycle and note how that effects the intensity of the LEDs.
• Use the second tri-colored LED and create a PWM circuit to drive this with other colors
• Use your PWM module for a single colored LED and vary the intensity

Describe your personal exploration activities

TA Notes and Feedback