As per the syllabus, the labs will be worth 30% of your final grade in the course.

This will be broken down as follows:

• Each lab will be worth an equal amount (2.5% of final grade)
• Each lab grade will be broken down into:
  • 80% pass-off
  • 10% online lab report, submitted through Learning Suite (20% for Lab 1 and 2)
  • 10% adherence to coding standard, source code submitted through Learning Suite (0% for Lab 1 and 2, which don't contain SystemVerilog code)

Read the SystemVerilog Coding Standard!

The TAs will apply the following grading rubric when evaluating your SystemVerilog source code. The goal is to get you in the habit of writing, readable, reusable, high-quality code. As such the TAs will be quite strict when grading your code.

• You start out with 100% credit (10 points) for the code-quality part of your grade.
• Each coding infraction reduces the code-quality credit by 1 point. Making the “same mistake multiple times” will result in losing multiple points. (eg. if your always_comb is missing default values for multiple signals assigned in the block, you will be deducted 1 point for each signal that does not have a default value).
• Your first 3 infractions are freebies. (ie. 5 infractions will results in a grade of 8/10)