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faqs [2020/05/07 14:57] ee220ta |
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| **Assigning a thinner signal to a wider signal**: What happens if I assign a k-bit signal to a k+n bit signal? In this case: | **Assigning a thinner signal to a wider signal**: What happens if I assign a k-bit signal to a k+n bit signal? In this case: | ||
| - | <code>logic [7:0] signalA; assign signalA = 1'b1;</code> signalA will be updated to 00000001. In general, the lower bit wide signal gets left padded out with zeros to the size of the wider signal. | + | <code Verilog>logic [7:0] signalA; |
| + | assign signalA = 1'b1;</code> | ||
| + | signalA will be updated to 00000001. In general, the lower bit wide signal gets left padded out with zeros to the size of the wider signal. | ||
