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| Both sides previous revision Previous revision Next revision | Previous revision | ||
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faqs [2017/09/25 18:53] electrovir added explanation for default nettype none requiring a net type on port declarations |
faqs [2020/05/07 14:57] (current) ee220ta |
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| **Nexys 4 clock speed**: 100 MHz | **Nexys 4 clock speed**: 100 MHz | ||
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| + | **Assigning a thinner signal to a wider signal**: What happens if I assign a k-bit signal to a k+n bit signal? In this case: | ||
| + | <code Verilog>logic [7:0] signalA; | ||
| + | assign signalA = 1'b1;</code> | ||
| + | signalA will be updated to 00000001. In general, the lower bit wide signal gets left padded out with zeros to the size of the wider signal. | ||
| + | |||
| =====Why isn't my simulation showing up?===== | =====Why isn't my simulation showing up?===== | ||
