`timescale 1ns / 10ps
//////////////////////////////////////////////////////////////////////////////////
//
//  Filename: tb_arithmetic.sv
//
//  Author: Brent Nelson
//  
//  Description: Provides a basic testbench for the arithmetic lab.  Is modified
//               version of tb_arithmetic v.
//
//  Version 2.1
//
//  Change Log:
//    v2.1: Removed btnl and btnr to streamline lab for on-line semesters.
//          Converted to SystemVerilog
//    v1.1: Modified the arithmetic_top to use "port mapping by name" rather than
//          port mapping by order.
//
//////////////////////////////////////////////////////////////////////////////////

module tb_arithmetic();

	logic [15:0] sw;
	logic [8:0] led;

    integer i,errors;
    logic  [31:0] rnd;
    logic signed  [8:0] A,B,result;
	
	// Instance the Seven Segment display
	arithmetic_top dut(.sw(sw), .led(led));

	initial begin

		errors = 0;
		#20
		$display("*** Starting simulation at time %t ***", $time);
		#20
	
		// Test 256 random cases
		for(i=1; i < 256; i=i+1) begin
			rnd = $random;
			sw[15:0] = rnd[15:0];
			A={sw[15], sw[15:8]};
			B={sw[7], sw[7:0]};
			result=A+B;
 			#20

			if (result != led) begin
				$display("Error: A=%b,B=%b and result=%b but expecting %b at time %t", A,B,led,result, $time); 
				errors = errors + 1;
			end
		end

		#20
		$display("*** Simulation done with %3d errors at time %t ***", errors, $time);
		$finish;

	end  // end initial begin

	
endmodule