https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/ 2026-05-18T08:35:10-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/ https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/lib/tpl/codowik/images/favicon.ico text/html 2017-09-06T16:20:06-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:7400_series_logic&rev=1504736406&do=diff 7400 Series Logic Devices History The 7400 series of logic ICs (integrated circuit) were an industry standard for logic for many years. These devices implement all the basic logic gates in a simple DIP (dual-inline package). A DIP is an electronic component with a rectangular housing and two parallel rows of connecting pins. Most 7400 series logic devices have 14 pins. text/html 2019-07-12T20:04:19-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:adding_an_xdc_file&rev=1562983459&do=diff Adding a Constraints File to your Project Like your SystemVerilog design files, the XDC file must be added to your project. Follow these instructions to add your .xdc file to your project. * Click on Add Sources just like in the Adding a SystemVerilog design module to a project tutorial. However, this time select text/html 2019-07-12T23:16:02-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:bitgen&rev=1562994962&do=diff Running the bitgen Design Step ---------- text/html 2018-01-10T16:25:52-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:changing_video_display&rev=1515626752&do=diff Changing the Video input on the Flat Panel Display The flat panel displays used in the digital lab can accept a video signal from multiple sources. There are two sources hooked up to the display: * Display Port: Attached to the video card on your desktop computer (default) text/html 2019-07-12T20:05:03-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:creating_a_new_module&rev=1562983503&do=diff Adding a SystemVerilog design module to a project This will show you how to add a new SystemVerilog source file to an existing project. You should make a new source file for every individual SystemVerilog module you make. Adding a New SystemVerilog File text/html 2020-02-03T16:30:49-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:digital_lab_overview&rev=1580772649&do=diff BYU Digital Laboratory Overview This video provides an overview of what to expect in the digital laboratory and a review of the policies and procedures. Please review the CAEDM lab policies which apply in this laboratory. ---------- TA Feedback text/html 2019-07-12T22:23:37-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:downloading_bitfile&rev=1562991817&do=diff Downloading a bit file to the Nexys 4 Board For labs 1 and 2, follow the instructions in the first section. For the remainder of the labs, follow the instructions in the second section. Downloading a bit file without a Vivado Project In the first two labs, you won't have yet created a project in Vivado, so you should follow these instructions to program the Nexys 4 board. From Lab 3 and later, follow the instructions in the section below. text/html 2017-09-05T17:23:25-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:downloading_to_the_nexys_4_using_adept&rev=1504653805&do=diff Downloading a bit file to the Nexys 4 Board Using Adept This will show you how to download a bit file to the Nexys 4 board by using the program called Adept. * First, check that your Nexys 4 jumpers are correctly placed by following the Setting Jumpers on the NEXYS 4 Board tutorial. text/html 2017-08-17T11:56:10-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:hierarchy_vivado_tutorial&rev=1502992570&do=diff Managing Hierarchy in Vivado * Discuss the concept of hieararchy. You manage hierarchy directly in your design files (instancing modules) * When you add files to Vivado using the “add file” command (link to tutorial), the Vivado design suite will analyze the design and try to recognize the hierarchy. text/html 2019-07-15T16:08:51-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:implementation&rev=1563228531&do=diff Running the Implementation Design Step ---------- TA Feedback text/html 2020-05-04T11:28:06-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:laboratory_instructions&rev=1588613286&do=diff Instructions for Completing ECEN 220 Laboratory Assignments It is essential that you carefully read through this in order to understand how to successfully complete a lab assignment. All labs follow a specific format and require the following: * text/html 2017-08-14T11:25:43-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:making_a_caedm_account&rev=1502731543&do=diff Creating a CAEDM Account In order to complete the laboratories in this class, you will need to have an account on the CAEDM computing system. CAEDM is the organization within the college of Engineering and Technology that manages the computing infrastructure and software that is used by all departments and schools in the college text/html 2018-06-25T11:50:17-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:making_an_xdc_file&rev=1529949017&do=diff Using Constraint Files (XDC) A Xilinx Design Constraints file or XDC file is needed to interface between your SystemVerilog modules and the NEXYS 4. It hooks up the inputs and outputs of your module to pins, buttons, LEDs, switches, etc. on the board. An XDC file is text/html 2017-08-16T17:01:50-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:nexys4&rev=1502924510&do=diff NEXYS4 Overview This video provides an overview of the NEXYS4 FPGA board you will be using in this course. NEXYS4 Reference Material: * NEXYS 4 Reference Manual * NEXYS 4 Schematic ---------- TA Feedback text/html 2017-08-14T11:28:03-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:printing_to_a_caedm_printer&rev=1502731683&do=diff Printing to a CAEDM Printer All lab computers can print to any of the CAEDM printers. How To * Enter the print setup like you would normally by clicking on file and then print. * Select CAEDM as the printer and click Print. * A login dialogue will pop up. Login with your CAEDM username and password. text/html 2020-06-04T12:37:28-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:putty&rev=1591295848&do=diff PuTTY Setup PuTTY is a serial console, a computer program that can listen for and display characters sent over a serial link. This is used in the UART labs so the NEXYS4 and the lab computer can communicate with each other over USB serial communication. text/html 2020-06-02T09:14:36-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:putty_personal_machine&rev=1591110876&do=diff Installing Putty on a Personal Machine PuTTY is a computer application that listens in to our board’s serial output. A serial protocol is one where the data to be transmitted bit-by-bit over a single wire. A number of our labs use that capability so you will need to have it available. text/html 2017-08-14T11:30:02-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:setting_up_the_nexys4_jumpers&rev=1502731802&do=diff Setting Jumpers on the NEXYS 4 Board This is how the blue jumpers should be set on your board. Do not turn on the board until you verify that the jumpers are set correctly. TA Feedback text/html 2018-01-25T09:38:55-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:simulation_screenshot&rev=1516898335&do=diff Capturing Simulation Screenshots You will be asked to create screenshots of your simulations for many of the laboratory assignments. This brief tutorial describes how to properly take a screenshot of your simulation for your laboratory report. When taking a screenshot of your simulation, include the following: text/html 2019-09-24T16:02:30-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:starting_vivado_simulation_tool&rev=1569362550&do=diff Starting the Vivado HDL Simulation Tool The Vivado design suite has a professional logic simulation tool that you can use to simulate the behavior of your SystemVerilog HDL files. HDL Simulation tools like this are used by professional engineers to simulate very complex and large digital design files. Your ability to use simulation tools effectively is key to successfully designing digital circuits. This tutorial will guide you through how to setup and start the Vivado simulation tool. Other t… text/html 2019-07-15T15:41:49-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:synthesis&rev=1563226909&do=diff Running the HDL Synthesis Tool An important step involved in the process of generating a digital circuit is HDL Synthesis. Synthesis is the process of converting the HDL files you have created into a set of logic gates and wiring. This set of gates and the wiring between them is called a circuit text/html 2020-02-05T14:00:35-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:tcl_tutorial&rev=1580936435&do=diff TCL Tutorial 1 The simulator is your best friend in debugging your modules, but it doesn't seem like it at first. This tutorial is designed to teach you some basic TCL commands and how to use them in the simulator. As you continue to use the simulator you will find additional shortcuts and tools that will make your job much easier. text/html 2018-09-24T16:26:02-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:tcl_tutorial_2&rev=1537827962&do=diff TCL Tutorial 2 In the previous tutorial, you learned about the three TCL commands that you will use for simulation. In this tutorial, you will learn about additional features that hopefully will make it easier to write TCL files. Additional add_force functionality text/html 2019-07-16T09:09:21-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:testbench_tutorial&rev=1563289761&do=diff Adding a Testbench and Simulating with a Testbench ---------- TA Feedback text/html 2018-01-10T14:53:18-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:timing_analysis&rev=1515621198&do=diff Vivado Timing Analysis When designing synchronous systems with a clock it is important to make sure that your circuit meets all of the timing constraints. The Vivado design suite have a number of tools to help you in the process of making sure your circuit meets the timing constraints. This tutorial summarizes the steps to take to add timing constraints and the timing analysis tools to check to see if your implemented design meets these constraints. text/html 2020-03-17T16:15:20-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:using_citrix&rev=1584483320&do=diff In order to facilitate lab participation, we will be using the Remote Software Citrix * There are instructions here to get Citrix, which will require you to login with your CAEDM login info (same info that you use to login to the lab computers). * Follow text/html 2017-09-06T16:50:17-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:using_the_breadboard&rev=1504738217&do=diff Building Logic Circuits on a Breadboard A breadboard is a construction base or board for prototyping electronic circuits. These boards allow you to easily create circuits without soldering wires or building a custom PCB (printed circuit board). Breadboards allow the creation of temporary connections between components that can easily be changed or removed. Although breadboards are great for rapid circuit prototyping, they are not very robust and may fall apart with too much use or rough handli… text/html 2017-08-14T11:29:08-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:using_the_caedm_scanner&rev=1502731748&do=diff Using the CAEDM Scanner The scanners in the CAEDM lab are the easiest to use. This will step you through how to use it. Below is a picture of it. The CAEDM is in room 425 of the Clyde. This scanner is in the back against the wall. * Emailing the file to yourself is the easiest way to scan a file. On the home screen tap text/html 2017-09-11T18:42:40-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:using_the_j_drive&rev=1505176960&do=diff Using CAEDM Storage (J Drive) Each CAEDM account holder has access to an online storage drive called the J Drive. Your J Drive can only be accessed by you. It is highly recommended that you use the J Drive for all your labs. Files saved on the J Drive will never be deleted whereas there is no guarantee that files saved on an individual lab computer will be there the next time you use it. text/html 2018-01-25T09:48:33-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:using_vivado_simulation&rev=1516898913&do=diff Using the Vivado HDL Simulation Tool Zoom to Fit A handy tool is the zoom to fit magnifying glass. After running commands, your simulation will often looks like just one solid like where nothing happened. Just click the zoom to fit magnifying glass to quickly fix your woes! text/html 2020-03-14T09:37:17-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:using_zoom&rev=1584200237&do=diff We will be using Zoom for Lab Instruction as well as TA Office Hours. * Go to BYU's Zoom Portal to login to your profile. (BYU IS Info has very straightforward instructions on how to download Zoom) * Zoom has comprehensive training videos that walk you through much of Zoom's basic functionality * The TA Schedule has individual links for joining each of the TAs Zoom Meetings. Use these links to get help from a TA during their posted hours. text/html 2017-08-07T16:56:02-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:videos&rev=1502146562&do=diff Videos This page contains the detailed scripts of the videos used in the tutorials. Adding Files and Syntax Checking Summary: with an empty project, you are ready to add your design file. * There are several ways to add a file. Summarize each of the video. text/html 2019-07-12T19:20:31-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:viewing_design_elaboration&rev=1562980831&do=diff Viewing SystemVerilog as a Schematic This will teach you how to view your SystemVerilog code as a schematic. This can be helpful in quickly finding simple errors or double checking that your code matches what you're trying to design. * First, set the module you want to view as a schematic as your top module. Find the module under text/html 2020-05-07T12:51:09-06:00 https://ecen220wiki.groups.et.byu.net/sp20/dokuwiki/doku.php?id=tutorials:vivado_project_setup&rev=1588877469&do=diff Creating a new Vivado Project The purpose of this tutorial is to guide you through the steps for creating a new project in the Vivado design suite for developing logic circuits for the NEXYS4 FPGA board. Clarifications to video steps for online courses: