BYU ECEn 220 labs

Arithmetic

2020-02-07T16:53:00-06:00

Arithmetic In this lab you will implement a two's complement binary adder and demonstrate the ability to perform binary addition, inversion, and subtraction. Learning Outcomes * Implement two's complement addition and subtraction * Develop a hierarchical design with three levels of hierarchy

Codebreaker

2020-06-08T09:29:51-06:00

Codebreaker In this lab you will be given a secret message that has been encrypted with a secret key. You will create a circuit that tries every possible key until you find out which key successfully decrypts the message. Your design will start searching for the key after the center button is pressed. The current key being tried is displayed on the LEDs, and your stopwatch from a previous lab is used to time how long it takes for you to find the correct key. Once you have discovered the sec…

Debounce State Machine

2020-04-30T09:44:18-06:00

Debounce State Machine You will create a debounce state machine and use this state machine to debounce the button on the NEXYS4 board to reliably count the number of times the button is pressed. Learning Outcomes * Understand how to debounce noisy input signals

Discrete Gates

2019-07-12T22:26:51-06:00

Discrete Gates In this lab you will apply your understanding of Boolean algebra and digital gates to implement two logic functions using discrete logic gates. You will interface your logic gates to the NEXYS 4 board and test your logic function with switches and LEDs on the board.

Lab 6 - Fun With Registers

2020-04-28T17:02:12-06:00

Lab 6 - Fun With Registers Prof Brent Nelson In this lab you will do some experimentation with flip flops to learn how they operate. You will create a single-bit loadable register, a 4-bit loadable register, and a counter. Learning Outcomes * Create a sequential circuit using FDCE flip-flop primitives

Introduction to Digital Systems

2020-05-11T08:05:46-06:00

Introduction to Digital Systems In this lab you will familiarize yourself with digital numbers, digital systems, and applications of digital systems by experimenting with the digital FPGA development board that you will use throughout the semester.

Lab Name

2017-07-03T11:11:37-06:00

Lab Name Learning Outcomes * List of specific learning outcomes Preliminary A set of activities that the student can perform before showing up to the lab to get started. Exercises Exercise #1 - Exercise Name Exercise #2 - Next Exercise

Pong: Part 1

2019-11-15T10:30:05-06:00

Pong: Part 1 This lab and the next lab work together to build a Pong game on the VGA display. In this lab you will create two modules, a ball drawer and a vertical line drawer. * Exercise 1: Designing a BallDrawer state machine on paper. * Exercise 2: Implementing the BallDrawer state machine in SystemVerilog, and verify with simulation.

Pong: Part 2

2019-12-03T16:26:09-06:00

Pong: Part 2 In this two-week lab, you will use your ball and line modules to make a Pong game. * Exercise 1: You will use your modules from Part 1 to draw a ball and two paddles on the screen. * Exercise 2: Make the ball bounce around the screen. (This exercise is the largest part of the lab)

Pulse Width Modulation

2019-03-18T11:44:48-06:00

Pulse Width Modulation The purpose of this lab is to create a circuit to drive a custom color on a tri-colored LED using “Pulse Width Modulation”. Learning Outcomes * Create a sequential circuit using behavioral SystemVerilog * Create a pulse-width modulated (PWM) controller

Register File

2019-07-17T15:14:46-06:00

Register File In this lab you will learn how to use sequential flip-flop circuits to build a 8×4 register file. Learning Outcomes * Create a sequential circuit using FDCE flip-flop primitives * Learn how to organize flip-flops into a register and register file

Seven Segment Decoder

2020-02-12T17:31:48-06:00

Seven Segment Decoder In this lab you will learn what a seven segment display is and how it works. You will create a digital circuit that drives a seven segment display with hexadecimal characters. Learning Outcomes * Learn how a seven segment display works.

Seven Segment Decoder (ALTERNATE)

2018-10-12T11:21:19-06:00

Seven Segment Decoder (ALTERNATE) In this lab you will learn what a seven segment display is and how it works. You will create a digital circuit that drives a seven segment display with hexadecimal characters. Learning Outcomes * Learn how a seven segment display works.

Seven Segment Controller

2019-05-30T12:59:51-06:00

Seven Segment Controller You will create an eight-digit seven-segment display controller using a sequential counter and dataflow SystemVerilog. Learning Outcomes * Be able to implement a counter using behavioral SystemVerilog and dataflow statements

Sp20 - Arithmetic

2020-05-14T13:08:28-06:00

Sp20 - Arithmetic In this lab you will implement a two's complement binary adder and demonstrate the ability to perform binary addition, inversion, and subtraction. Learning Outcomes * Implement two's complement addition and subtraction * Develop a hierarchical design with three levels of hierarchy

Codebreaker_serial

2020-06-11T10:18:04-06:00

Codebreaker_serial Overview In this lab you will be given a secret message that has been encrypted with a secret key. You will create a circuit that tries every possible key until you find out which key successfully decrypts the message. Your design will start searching for the key after the center button is pressed. The current key being tried is displayed on the LEDs, and your stopwatch from a previous lab is used to time how long it takes for you to find the correct key. Once you have d…

Sp20 Debounce State Machine

2020-05-28T18:42:46-06:00

Sp20 Debounce State Machine You will create a debounce state machine and use this state machine to debounce the button on the NEXYS4 board to reliably count the number of times the button is pressed. Learning Outcomes * Understand how to debounce noisy input signals

Sp20 Lab 6 - Fun With Registers

2020-05-19T13:23:18-06:00

Sp20 Lab 6 - Fun With Registers Prof Brent Nelson In this lab you will do some experimentation with flip flops to learn how they operate. You will create a single-bit loadable register, a 4-bit loadable register, and a counter. Learning Outcomes

Sp20 Lab 1 - Installing on Your Computer

2020-05-10T00:02:34-06:00

Here are the notes we went over from the first day of lab meeting... Sp20 Lab 1 - Installing on Your Computer Your job for this lab is to select how you intend on working with Vivado during the semester and then do the installation for that method.

Sp20 - Introduction to Digital Systems

2020-05-04T11:38:02-06:00

Sp20 - Introduction to Digital Systems In this lab you will familiarize yourself with digital numbers, digital systems, and applications of digital systems by experimenting with the digital FPGA development board that you will use throughout the semester.

Sp20 - Seven Segment Decoder

2020-05-14T12:58:13-06:00

Sp20 - Seven Segment Decoder In this lab you will learn what a seven segment display is and how it works. You will create a digital circuit that drives a seven segment display with hexadecimal characters. Learning Outcomes * Learn how a seven segment display works.

labs:sp20_stopwatch

2020-05-19T17:08:32-06:00

Sp20 Stopwatch In this lab you will create a digital stopwatch. As shown in the video below, the stopwatch will be displayed on the eight-digit seven-segment display. * Digits 7:6 will display minutes, digits 5:4 will display seconds, and digits 3:0 will display ten-thousandths of a second.

Sp20 - Structural SystemVerilog

2020-05-07T11:55:57-06:00

Sp20 - Structural SystemVerilog In this lab you will implement several logic functions using the SystemVerilog HDL (Hardware Description Language). You will simulate your SystemVerilog designs using commercial simulation tools and synthesize them into circuits that will be downloaded onto the NEXYS 4 board.

Sp20 UART Receiver

2020-06-10T17:08:03-06:00

Sp20 UART Receiver In this laboratory you will create and test the receiver part of a UART. Your design will closely follow the serial transmitter you previously did. That is, you will have handshaking with a host (but the signals are called Receive and Received). And, the receiver has similar components - a state machine, a bit counter, and a timer.

Sp20 UART Transmitter

2020-06-02T13:28:15-06:00

Sp20 UART Transmitter In this laboratory you will create an asynchronous serial transmitter that will allow you to send ASCII characters from the NEXYS4 board to your computer. Learning Outcomes * Learn how to implement state machines using behavioral SystemVerilog

labs:stopwatch

2020-05-18T11:18:00-06:00

Stopwatch In this lab you will create a digital stopwatch. As shown in the video below, the stopwatch will be displayed on the eight-digit seven-segment display. * Digits 7:6 will display minutes, digits 5:4 will display seconds, and digits 3:0 will display ten-thousandths of a second.

Structural SystemVerilog

2020-04-20T14:35:42-06:00

Structural SystemVerilog In this lab you will implement several logic functions using the SystemVerilog HDL (Hardware Description Language). You will simulate your SystemVerilog designs using commercial simulation tools and synthesize them into circuits that will be downloaded onto the NEXYS 4 board.

labs:testdev

2020-01-28T14:24:44-06:00

* Use the following circuit: * Use the following circuit:

labs:testinga

2020-05-11T08:05:58-06:00

abasdfasdff asdf asdf asdf asdf asdf asdf

UART Receiver

2019-04-09T11:47:03-06:00

UART Receiver In this laboratory you will create an asynchronous serial receiver that will allow you to send characters from your computer to the NEXYS4 board. Your design will closely follow last week's serial transmitter. That is, you will have handshaking with the receiver (but the signals are called Receive and Received). And, the receiver has similar components - a state machine, a bit counter, and a timer. A number of the details are different but it will have a similar organization.

UART Transmitter

2020-04-30T09:46:13-06:00

UART Transmitter In this laboratory you will create an asynchronous serial transmitter that will allow you to send ASCII characters from the NEXYS4 board to your computer. Learning Outcomes * Learn how to implement state machines using behavioral SystemVerilog

UART Receiver

2020-04-13T11:30:49-06:00

UART Receiver In this laboratory you will create and simulate the receiver part of a UART. Your design will closely follow last week's serial transmitter. That is, you will have handshaking with a host (but the signals are called Receive and Received). And, the receiver has similar components - a state machine, a bit counter, and a timer.

Sp20 Lab 1 - Installing on Your Computer

2020-05-10T00:12:22-06:00