BYU ECEn 220

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2020-05-09T23:58:35-06:00

FAQs and Tips

2020-05-07T14:57:59-06:00

FAQs and Tips General questions, their answers, and tips for ECEn 220. Default net type: Verilog will default your signals to a 1 bit wire if you don't declare them as anything. This can mess you up when you have typos! To prevent this from happening, put

Lab Grading

2019-09-10T15:24:26-06:00

Lab Grading As per the syllabus, the labs will be worth 30% of your final grade in the course. Grade Breakdown This will be broken down as follows: * Each lab will be worth an equal amount (2.5% of final grade) * Each lab grade will be broken down into:

Labs

2018-07-16T10:20:00-06:00

Labs Lab Details Lab 0: Introduction Explanation of lab requirements and processes Lab 1: Breadboard Introduction to the breadboard and IC chips Lab 2: Oscilloscope Introduction to the oscilloscope Lab 3: Verilog, Simulation, and Downloading Introduction to Structural Verilog and Vivado Lab 4: Arithmetic Logic Unit Advanced Structural Verilog Lab 5: Seven Segment Display Introduction to Dataflow Verilog

Tips on Working Remotely

2020-03-24T17:34:16-06:00

Tips on Working Remotely Tips we have learned collectively while working remotely will be put here... “” LabConnect * Do NOT work on the C: drive - if you get disconnected you will never get back to that specific machine to find your files.

Resources

2020-06-04T13:31:25-06:00

Resources Constraints * [Master XDC File] Design Helps * Combinational Logic Styles * Common Warnings and Errors * Common TCL Commands * Using TCL for Fame and Fortune Documentation * NEXYS 4 Reference Manual * NEXYS 4 Schematic Modules * Seven Segment Controller * VgaDrawer Module * CharDrawer Module * CharDrawer_serial Module * RC4 Encryption/Decryption Module Other * Accessing the Vivado Tools * Textbook links and errata * FAQs and Tips

sidebar

2020-06-08T09:14:28-06:00

* Home Page * * Tutorials * Resources * Creating Vivado Projects * Taming Vivado * Simulator Hints * TA Schedule * Sp20 L1 - Install * Sp20 L2 - Board Intro * Sp20 L3 - Structural SV * Sp20 L4 - Arithmetic * Sp20 L5 - Seven Segment * Sp20 L6 - Fun With Registers * Sp20 L7 - Stopwatch * Sp20 L8 - Debouncer * Sp20 L9 - Uart Transmitter * Sp20 L10 - Codebreaker_serial * Sp20 L11 - Uart Receiver * * Lab 1 - Introduction * Lab 2 - Discrete Gates * La…

Simulator Hints

2020-03-10T14:57:57-06:00

Simulator Hints Some things that can help with simulation: 1. Interactive Simulation There is no need to push the “Run All” button when simulating. You can always run for 2000 ns, look at the waveforms, and repeat. For some labs, running the entire testbench can take 15 minutes - don't blindly click Run All.

Using Vivado During Spring 2020

2020-09-02T17:06:55-06:00

Using Vivado During Spring 2020 You will use the Xilinx Vivado design software to design digital circuits and then test those designs on the circuit board. This is a very large, commercial software package that is being provided free of charge for your use. Options for using this to complete the labs include the following (sorted from most preferable to least preferable).

BYU ECEn 220 Wiki

2020-05-10T00:14:38-06:00

BYU ECEn 220 Wiki Welcome to the Wiki page for the BYU ECEn 220, Fundamentals of Digital Systems course. This wiki contains all of the materials needed to complete the laboratory assignments for the course. Note the sidebar on the left with links to the labs and other laboratory resources.

ta_schedule

2020-06-15T17:03:49-06:00

TA HOURS WILL BE HELD ON ZOOM, NOT IN THE LAB If you see the “ Lucy” next to an entry below, it means the Zoom meeting is going - so please join! Scheduled Class Lab Hours Zoom Link: Ben Fogg TA Hours: Ammon Wolfert TA Hours: Jarom Harris TA Hours

Testbenches: An Alternative to Tcl

2020-03-17T08:58:54-06:00

Testbenches: An Alternative to Tcl Prof. Brent Nelson 3/2020 The most common way to simulate a SystemVerilog design is actually to write a testbench in SystemVerilog and use it to drive values into your design and monitor the outputs for correctness. For example, that is what all the testbenches you are given in the various labs do themselves.

Tutorials

2020-05-26T16:10:49-06:00

Tutorials This page contains an index to all of the tutorials in each of the labs. You will likely need to refer to these tutorials more than once as you complete the labs in the class. Lab 1 - Introduction to Digital Systems * Instructions for Completing ECEN 220 Laboratory Assignments * Creating a CAEDM Account * Using CAEDM Storage (J Drive) * Printing to a CAEDM Printer *

Using TCL for Fame and Fortune

2020-02-07T15:22:00-06:00

Using TCL for Fame and Fortune If you hate to type repetitive TCL commands to exercise your design, here are some ideas. It turns out TCL is a full-featured programming language (even if it is verbose and perhaps clunky). But, once you find some examples to cannibalize, it can be pretty easy to create very compact simulation scripts.

SystemVerilog Coding Standards

2020-05-11T17:30:54-06:00

SystemVerilog Coding Standards HDLs (Hardware Description Languages) like SystemVerilog can be difficult to understand. To make SystemVerilog code more readable and maintainable, you are required to follow coding standards. These standards are explained below. Each lab will be graded against this coding standard.

Taming Vivado

2020-05-28T14:35:15-06:00

Taming Vivado As with all software, Vivado has a number of “features” which you will sometimes have to deal with. This page is to help with a number of commonly encountered issues you may need to understand. 1. General Errors Sometimes your design will not compile and gives elaboration errors. How to debug this case?

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2020-05-09T23:44:04-06:00

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