This will teach you how to view your SystemVerilog code as a schematic. This can be helpful in quickly finding simple errors or double checking that your code matches what you're trying to design.
If you make changes to your SystemVerilog code after opening the elaborated design, you need to update the schematic. To do so, right click on Elaborated Design and click Reload Design.
A bar near the top of the Vivado window may also appear stating that the elaborated design is out-of-date. Clicking Reload on this bar will also successfully refresh the schematic.