====== Adding a Testbench and Simulating with a Testbench ======
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/* {{ :tutorials:adding_testbenches.mp4 }} */
/*
* Goal of tutorial:
* Review what happens when you added design projects. they show up in the "Design sources" folder of your project.
* In addition to the design sources folder, they also appear in the "simulation sources" folder. They are here because in addition to synthesizing these files, you will be simulating these files.
* Note that the seven_segment_top file is bold indicating that when you simulate, you will simulate this file and the other file will simulate as a sub-module
* You can change which file is set as "top". (show this).
* In addition to design sources, you can add simulation sources or testbenches. A testbench file is a verilog file that provides a stimuls to your synthesizable verilog file but it is not synthesizable itself. To add a file that you simulate but do not synthesize, you add it as a "simulation source". Show them how to do this.
* See the color of the file. Make sure the testbench is black (set as top)
* Make sure the hierarhcy is correct simulation sources section
* Problems that can happen (mismatch hierarchy)
* Note that the file shows up in simulation sources but not in design sources
* Simulating different levels of hierarchy
* Go through the process of simulation
* Start it the same way
* Not forcing the signals - it will do the forcing.
* Just execute a "run" (run 1 us)
* Notice hierarchy
* Notice the console (printing messages)
* Will indicate errors (show them)
* Wait for "done" message
* Show them how to find a time in he simulation
*/
/*
===== Adding an Testbench file with a TCL command =====
You can add your testbench file to your project with the following TCL command:
add_files -fileset sim_1 -norecurse C:/wirthlin/ee220/git/labs/SevenSegment/testbench/tb_SevenSegment.v
*/
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