====== Running the HDL Synthesis Tool ======

An important step involved in the process of generating a digital circuit is HDL //Synthesis//. Synthesis is the process of converting the HDL files you have created into a set of logic gates and wiring. This set of gates and the wiring between them is called a circuit "netlist". The following video demonstrates how to run the Synthesis tool.

{{youtube>bthZAsSfZNQ?rel=0&noborder&1080x700}}

/*
{{:tutorials:synthesis.mp4}}
*/

/*


Pictures that explains the synthesis tool:
  * Screen shot of pressing the "Run Synthesis" tool
  * Screen shot of top right corner (Running synth_Design) - takes time
  * Screen shot of top right (Synthesis complete). Also show the dialog box on what to do next.

Video Synthesis Report:
  * Show them the message window (review). Add a message intentionally.
  * Show them how to get this report 

After successfully completing the synthesis process, you can view a schematic of your circuit. This circuit schematic will be different from the one that you obtained in an earlier "RTL Elaboration" step and is mapped to the circuit primitives of the FPGA. 

  * Show them how to get the schematic ("schematic" icon)

*/

/*
===== Using a TCL Command to Initiate Synthesis =====

The syntheiss

<code>
launch_runs synth_1
</code>
*/

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