=====Behavioral Verilog=====

Behavioral Verilog allows you to change the way in which you conceptualize your hardware. Most especially, Behavioral Verilog makes creating **sequential circuits** a breeze. For full explanations and details, read the textbook. ((Appendix C))

====Reg====

The **reg** keyword is used when declaring a port and causes that port to become a flip flop or register. You don't need to build the whole master slave flip flop design with gates. You must store values in one of these using the **Always Block** which is explained in the next section.
\\
<color maroon>Example:</color> ''output reg q;'' creates a register whose current value is the output port ''q''.

You can also have standalone registers internal to a module that aren't used as output ports.\\
<color maroon>Example:</color> ''reg q;'' creates a register inside the module whose value is not an output port but may be used internally for other purposes.

====Always Block====

The always block creates a block of sequential code. When you make an Always Block you must specify a signal that will trigger that block and the edge type for the trigger. **posedge** is for the positive or rising edge, **negedge** for the negative or falling edge. This trigger signal will often be the **clock,** but it can be any signal. If no edge value is given, the always block will be triggered whenever the given signal changes.

The always block also allows the use of **if** statement blocks (like in nearly every other language, yay!), and a new assignment operator: ''%%<=%%''.

The syntax for all of this will be explained through the following example. This example is simple d flip flop with a clear signal.

<code Verilog>
  input clock, clear, d;
  output reg q;
  
  always @(posedge clock)
    if (clear)
      q <= 0;
    else
      q <= d;
</code>

**output reg q** operates as explained earlier. A port **must** be a reg to be assigned a value inside an always block. \\
**always @(posedge clock)** is the syntax for beginning an always block. **posedge clock** specifies that the always block will be triggered on the positive edge of the input **clock**. \\
**if** statements work pretty much like they do in any C style language. \\
**%%<=%%** must be used in assigning values inside an always block.

If an **always** or **if** block only contains 1 statement (an **if-else** is a single statement) then no special syntax is needed. However, if any more statements are contained in the always block, **begin** and **end** must be used to encapsulate it all.

The following example will show this. This example also demonstrates how Behavioral Verilog, like the other forms of Verilog, is not sequential. If you don't remember what this is talking about, see the [[tutorials:old:structural_verilog#verilog_execution]] section of the [[tutorials:old:structural_verilog]] tutorial. This is a slight variation of an example give in the textbook. ((Page 281))

<code Verilog>
  input clock, clear, in;
  output reg out;
  reg a, b;
  
  always @(posedge clock)
    if (clear)
    begin
      a <= 0;
      b <= 0;
      out <= 0;
    end
    else
    begin
      a <= in;
      b <= a;
      out <= b;
    end
</code>

**begin** and **end** act like curly braces in C-style languages. As explained above, they are necessary if your **always** or **if** have more than one statement inside them. Note than an if else statement counts as 1 statement, and the always block does not need begin or end. Else if can also be included in an if else statement and it will still be a single statement.

<code Verilog>
  a <= in;
  b <= a;
  out <= b;
</code>

Shows how Verilog is not sequentially executed like software programming languages are. The register for **b** is not overwritten by **a** before it is stored on **out**.