======Initialization======

This is a further explanation of behavioral verilog, if you have not reviewed the [[tutorials:lab_7:behavioral_verilog |behavioral verilog tutorial]] yet it is recommended that you do so.

Registers are made with the key word <color magenta> reg </color> and hold any values they are given until given a new value.  However, they do not automatically start with a value.  In other words there is no automatic initialization.  There are a couple of ways to give them an initial value.  The first way is to reset or clear upon startup which should have the functionality of setting the reg value to 0 in your code.

The other way to initialize a reg is give the reg a value when it is declared (see the code below).  This allows the <color magenta> reg </color> myreg to have all 20 of its bits assigned a value from the very start. 


<code Verilog>
  input clock, clear;
  input [3:0] d;
  output [3:0] q;
  
  reg [19:0] myreg = 20'b00011111111111111011;
  
  always @(posedge clock)
    if (clear)
      myreg <= 20'b0;
    else
      myreg <= myreg + d;
      
  assign q = myreg[19:16];
</code>

Notes: This is a type of counter that increments by 0-15 depending on the value of d. The output is the top 4 bits of myreg which can easily be converted to hexadecimal value.  Notice how the value used to initialize myreg is close numerically to a change in the output value.