=====Circuit Timing=====

This tutorial will briefly introduce the concept of circuit timing by explaining **gate delay**, the **clock**, **flip flops**, and **sequential logic**.  This is not meant to teach a complete understanding of these given topics, but it should be enough to properly prepare you for lab 2.  These concepts will be taught more thoroughly in later chapters of the textbook.((Chapters 10-14))

====Gate Delay====

When using any of the logic gates (and, or, not, etc.) in hardware, there is a short amount of time before a gate's output responds to changes in its inputs.  

This short amount of time is called a **gate delay**.  Typical delay times used by the textbook are around 3-7 nanoseconds.((Page 115))  Actual gate delay will vary based on implementation.

{{ :tutorials:circuit_timing:gate_delay_clock.png?nolink |}}

Here's a visual of the output **lagging** after the input to an and gate is changed:

{{ :tutorials:circuit_timing:animated-gate.gif?nolink |}}

Gate delays restrict how fast a circuit will be.  Some gates have longer delays than others.

====Clock====

The clock is a signal, generated by the device you're using, which is a square wave with extremely accurate and consistent timing.  A **square wave** alternates between the values 0 and 1 over time and looks like this:

{{ :tutorials:circuit_timing:square_wave.png?nolink |}}

Many components depend on the clock.  These components use the **positive or negative edges** of the clock's waveform to trigger various operations.  These are also called **rising or falling edges** respectively.  The following diagram highlights the negative and positive edges:

{{ :tutorials:circuit_timing:clock_wave_highlighted_edges.png?nolink |}}

Nearly everything you design will depend on a clock.  Thus, the **clock speed** (or frequency) is a critical consideration.  The Nexys 4 board you will use has a clock speed of 100 MHz.  Some personal computers have a clock speed of 4 GHz or more!

====Flip Flop====

A **flip flop** is a simple memory storage device. A single flip flop stores one bit and thus can hold the values of **1** or **0**.  Here is the diagram for a flip flop: ((Page 140))

{{ :tutorials:circuit_timing:flop.png?nolink |}}

The input **D** is the wire whose value will be stored on the flip flop.  \\
The output **Q** always holds the current value which the flip flop is storing.  \\
The input **clr** (short for clear), when turned on, will set the value stored in the flop to 0, no matter what D or Q are. \\
The triangle on the bottom is where the **clock** signal should be hooked up.

What makes a flip flop useful is that it will only store the value of the input D on the **clock edge** (generally the positive clock edge).  In between clock edges, the flip flop will not store D's value and the output Q will therefore remain the same.  Once the next clock edge occurs, it will again store the value of D in the flip flop.

A flip flop's internals are made up of gates.  Therefore, because of **gate delay**, as explained earlier, a flip flop also has a delay from the clock's edge to when D is stored in the flip flop.  You will learn the details of a flip flop's design and timing later in the class. ((Chapter 11))

The current value of a flip flop or a group of flip flops is referred to as the current **state**.

====Sequential Logic====

Because of memory storage components such as the flip flop, you can now make circuits where the next state of a circuit is dependent on the current state.  This is called **sequential logic**.((Chapter 13))  

A simple example is a counter device that counts from 0 to 10.  Say the counter will count up by 1 on every positive clock edge.  How do you calculate the next state of a simple counter such as this?  It's just the current state + 1.  The **next state** is dependent on the **current state** and it is therefore sequential logic. (Combinational logic is simple gates that merely depend on whatever is given to their inputs.  It does not depend on previous values.)

You will not be building a sequential circuit yourself in the oscilloscope lab, but you will analyze the effects of gate delay on a already built sequential circuit.