===== Adding a SystemVerilog design module to a project=====

This will show you how to add a new SystemVerilog  source file to an existing project.  You should make a new source file for every individual SystemVerilog module you make. 


{{youtube>6jQm4zmJC7g?rel=0&noborder&1080x700}}


==== Adding a New SystemVerilog File ====


  - First, click **Add Sources**.  This button is located in multiple places.  (See video above)
/* Here are some of them: \\ {{:tutorials:creating_verilog_module:add_sources_1.png?nolink&300|}} {{:tutorials:creating_verilog_module:add_sources_2.png?nolink&300|}} {{:tutorials:creating_verilog_module:add_sources3.png?nolink&300|}}
*/
  - This will open the New Source Wizard. Click **Add or create design sources** then **next**.
  - Click **Create File**. \\  Change the File Type to **SystemVerilog** and choose where you want to save the new file. Enter a name for the file and click **OK**. \\ You can add more files before going to the next step if you want, but you can also do so any time later. Click **Finish** if when you're done adding files.
  - Now you can enter all the port information for each module you're adding.  You can type it all in the prompt they give you, or just click **OK** (and then **Yes** if you didn't modify anything) to type it in yourself in the SystemVerilog file.  When you're done, click **OK**.
  - Now your new source(s) will be available in the **sources** pane under **Design Sources**.  (They will also be visible under **Simulation Sources**.) To edit one of your sources, find the file in the **sources** pane and double click it to open it.

Make sure you **save your SystemVerilog file often**, especially before running a simulation or generating a bitstream file.

====Adding a Previously Created Module====

/* {{ :tutorials:creating_verilog_module:vivado_add_external_source.mp4| }} */

This probably won't be useful in early labs but will be necessary in the later ones. This steps you through adding a source file that you have previously made (either in a past lab, or downloaded from the course website).

  - Go through steps 1 and 2 in the section above.
  - Instead of clicking Create File, click **Add Files**.
  - Browse to the location of the source file you wish to add. 
    - If you created the source in Vivado, and saved the file internal to the project, you'll have to navigate to that project's folder, then to the subfolder named **<project name>.srcs** then **sources_1** then **new**.
  - Make sure the "Copy sources into project" checkbox is marked.
  - Click **Finish**.

/*
==== Adding a file using TCL commands ====

You can add a file to your project with a simple TCL command on the command line. The syntax for adding a SystemVerilog design file is as follows:

<code>
add_files <file_name>
</code>

*/
----

[[ta:tutorials#add_file_tutorial|TA Feedback]]