====== Simulator Hints ======
Some things that can help with simulation:

=== 1. Interactive Simulation ===

There is no need to push the "Run All" button when simulating.  You can always run for 2000 ns, look at the waveforms, and repeat.  For some labs, running the entire testbench can take 15 minutes - don't blindly click Run All.

Related to the above, with tesbenches provided for you to use, if there is an error that gets printed, hit the pause button at the top of the screen (looks like ||) rather than wait another 10 minutes for the Run All to complete.  You can then immediately start debugging.

Related to the above, you can type Tcl commands into the Tcl command line area - use it!  Rather than make little changes to your Tcl files and then re-run the entire simulation, just start typing commands into the Tcl command line.  Reset your circuit, apply inputs, and run for a bunch of ns.  This is far superior to restarting from scratch every time you need to make a change to your Tcl file.  It makes debugging interactive...

=== 2. Visibility is EVERYTHING !!!!===
If the top level signals in your design aren't working it may be due to something inside your other modules.  And, if you cannot see what is inside your other modules in the waveform view, how in the world could you ever debug it?   If you timer is not working is it a) because it is not being told to increment?, b) because it is never reset?, or c) something else?  Watching it and its inputs will allow you to figure that out immediately.

So, once the simulation has started but before you click Run All, click the "Scope" tab next to sources and drag your other modules into the waveform viewer.  It will make their signals visible in the waveform view and you should be able to tell where the problem is in your code both a) immediately and b) without guessing.

You can never have too much visibility into your circuit.