====== Common TCL Commands ======

This page provides a brief summary of common TCL commands that may help you during your laboratory assignments.

^ Project Management ^^
^ Command ^ Description ^
| create_project | Create new Vivado Project |

===== Project Management =====


** Creating a new project **

<code>
create_project <project name> <Path of project> -part xc7a100tcsg324-1
</code>

** Adding a Verilog file to the project **

<code>
add_files -norecurse C:/wirthlin/ee220/git/labs/StructuralVerilog/solution/TestFunction.v
update_compile_order -fileset sources_1
</code>

** Adding a constraints file (.xdc) to the project **

<code>
add_files -fileset constrs_1 -norecurse <filename.xdc>
</code>

===== Simulation =====

** Start the simulation **
<code>
launch_simulation
</code>

** Exit the simulation **
<code>
close_sim
</code>

** Restart the simulation **

This restarts the simulation at time t=0 without exiting the simulation. You may want to run this command if you want to start the simulation over without relaunching the simulation tool.

<code>
restart
</code>

** Run the simulation **

<code>
run 10 ns
</code>

** Force a value on a signal **

<code>
add_force <signal_name> <value>
</code>
===== RTL Analysis =====

** Generate schematic of RTL design: **

<code>
synth_design -rtl -name rtl_1
</code>

** Close schematic of RTL design: **

<code>
close_design
</code>