====== Structural SystemVerilog ======

In this lab you will implement several logic functions using the SystemVerilog **HDL** (Hardware Description Language). You will simulate your SystemVerilog designs using commercial simulation tools and synthesize them into circuits that will be downloaded onto the NEXYS 4 board.

===== Learning Outcomes =====

  * Describing circuits using SystemVerilog.
  * Use the Vivado design suite for project creation.
  * Use Vivado simulation and synthesis tools.
  * Learn to create TCL simulation scripts.

===== Preliminary =====
  * Review Chapter 8 of the textbook (you will need to be familiar with SystemVerilog before starting this lab).
  * This laboratory will involve a //lot// of tutorials. You may want to start working through these tutorials before you arrive at the laboratory to get a head start.

===== Exercises =====

==== Exercise #1: Creating a Vivado Project ====

Many software tools are needed to convert your SystemVerilog file into a configuration bit file that you can download onto an FPGA device. We will be using a set of tools called **Vivado** developed by Xilinx, the manufacturer of the FPGA devices in the lab. You will use Vivado throughout the rest of the semester.

  - Create a new Vivado project by following the instructions in the [[tutorials:vivado_project_setup]] tutorial.  __Make sure you follow the steps in red to properly configure the error messages in your project.__
  - Now, create a new SystemVerilog file to hold a module by following the instructions in the [[tutorials:creating_a_new_module]] tutorial.  Your module will be called "FourFunctions".  Do not add any ports to it in this exercise, you just want an empty module definition.
    

==== Exercise #2: Implement Logic Functions in Structural SystemVerilog ====

In this exercise you will create the //structural// SystemVerilog description of four logic functions. Note that you must use structural SystemVerilog rather than Dataflow SystemVerilog to complete this assignment. Follow the steps below to begin this exercise.

  - Open up the FourFunctions.sv module you created in Exercise #1 by double-clicking it in the figure you just saw above. 
  - Start your file by creating a **header** in your SystemVerilog file that conforms to this class's [[:verilog_coding_standards]].  If Vivado has pre-populated the file with header information you are free to remove that or modify it (do not delete the first line that contains `timescale 1ns / 1ps, however.  Either way, your design must have a **header** that conforms to the class's [[:verilog_coding_standards]]
  - NOTE: the coding standards are very specific on how to declare the inputs and outputs of modules.  If you read carefully, you will note that they require the inclusion of the word "wire" in certain places.  This is not reflected in the textbook examples.  The need to include this is due to specific requirements of Vivado when the `default_nettype none macro directive is included.)
  - Now, define a module named "FourFunctions" with the following ports. Make sure to match everything described below exactly (including the port names).  

NOTE: if you are fuzzy on module declarations, consult the textbook.  In particular, review Sections 8.3, 8.4, and 8.6.1 in the textbook.  And, just remember that due to our using Vivado, you also need to include the word "wire" in certain places.  Consult the [[:verilog_coding_standards]] for details on that.  

Finaly, at this point remember there is no reason to get creative - just copy the structure and syntax (including indentation) of the code examples in the book sections noted.  And, carefully follow the coding standard.  This goes for this lab as well as all future labs.  

**Module Name**: FourFunctions

^ Port Name ^ Size (bits) ^ Direction ^
| A | 1 | Input |
| B | 1 | Input |
| C | 1 | Input |
^  ^ ^
| O1 | 1 | Output |
| O2 | 1 | Output |
| O3 | 1 | Output |
| O4 | 1 | Output |

Implement the following //four// logic functions inside of this module.

  * **O1**: O1 = AC+A'B

  * **O2**: O2 = (A+C')(BC)

  * **O3**: The logic function below: 

{{:labs:simpleschem.png?400|Function for O3}}

  * **O4**: The logic function below: 
{{:labs:hwb.png?300|Function for O4}}

If these functions require intermediate signals (signals that are not module ports), you will need to declare them using the 'logic' keyword (see text for details).  Also, choose meaninful names or (probably better yet) put a comment above them to tel what they are used for.

You do not need to minimize these functions, just implement the logic functions directly using basic gates (AND, NAND, OR, NOR, NOT, etc).

As you type and save your SystemVerilog code, Vivado will identify syntax errors in the code.  Edit the code until there are no syntax errors.

With no syntax errors in your HDL code you can perform **elaboration** and generate a notional schematic of the circuit. Follow the [[tutorials:viewing_design_elaboration]] tutorial to view a schematic of your code.

Although it is difficult to find logic errors in the schematic view, it is easy to see problems such as missing connections between the gates, inputs, and outputs. Look for unconnected top-level ports or missing connections in your gates (missing connections are annotated with **n/c** on the schematic).

**Exercise 2 Pass-off:** Review your code with a TA as well as your circuit schematic (the schematic under "RTL Analysis"). Be able to explain what each of the components are and how Vivado has implemented your four functions.\\ \\

/* I think it would be useful to add a question that asks them to compare the schematic to their logic functions. In particular, it would be useful to have them create a logic equation for each output based on the gates that were chosen. Then, have them prove that the logic equations are the same. This may be difficult to do in learning suite but it is an interesting exercise for them to complete.
*/

==== Exercise #3: SystemVerilog Simulation ====

Simulating your design is //the most important phase of digital logic design//. You will do extensive simulations of all your digital circuits and it is very important that you learn how to use the logic simulation tools. 

Why is it so important to learn to use the simulator? Finding errors in your design in simulation may take seconds or minutes, whereas finding those same errors in your physical circuit after it is running on the FPGA board may take hours. !!!  The greater skill you have at using these simulation tools, the easier and more successful you will be in all future labs.

Complete the following steps for this exercise:

1. Begin the simulation process by following the [[tutorials:starting_vivado_simulation_tool]] tutorial.

2. Read through this [[tutorials:tcl_tutorial|tutorial]] to get a feel for the TCL commands you will be using. Then, create a .tcl file and simulate your module by issuing a number of **add_force** commands. 

The following .tcl code snippet demonstrates one way to simulate two of the eight input combinations. In your own .tcl file you will need to make sure to test all possible input combinations.
<code>
# Comments are written with the '#' character instead of // or /**/.
 
# Simulate A=0, B=0, C=0 for 10 ns
add_force A 0
add_force B 0
add_force C 0
run 10 ns

# Simulate A=0, B=0, C=1 for 10 ns
add_force A 0
add_force B 0
add_force C 1
run 10 ns
</code>

3. Compare the resulting waveform with a truth table for your four functions. Verify that your simulation outputs match the expected outputs. If there are errors, fix your SystemVerilog file and simulate again until your circuit operates as intended.

**Exercise 3 Pass-off:** Show a TA your simulation and explain how you know that your circuit is working correctly. The TA will also check your tcl commands to see if you have tested all possible input combinations.\\ \\


==== Exercise #4: Synthesis and Implementation ====

During this exercise you will translate your SystemVerilog HDL file into an actual digital circuit that can operate on the FPGA device. There are three specific steps you must complete in order to perform this translation. These steps include:
  - HDL Synthesis,
  - Implementation, and
  - Bitfile Generation
This exercise will describe each of these steps and guide you through the process of completing these steps for your design. 

=== Creating a Constraints File ===

Before proceeding with the first "HDL synthesis" step, you must create a constraints file, or **XDC** (Xilinx Design Constraints) file. This tells the synthesis tool which pins on the FPGA board are being connected to which inputs and outputs of your circuit. **Without this file, your design will not be able to synthesize even if your circuit is logically correct.** This table shows the mapping we will use for this module.

^ Port Name ^ Pin ^ NEXYS 4 ^
| A | M13 | Switch 2 (SW2) |
| B | L16 | Switch 1 (SW1) |
| C | J15 | Switch 0 (SW0) |
| O1 | N14 | LED 3 (LD3) |
| O2 | J13 | LED 2 (LD2) |
| O3 | K15 | LED 1 (LD1) |
| O4 | H17 | LED 0 (LD0) |

For example, this table indicates that the "A" input to your logic circuit should be mapped to pin "M13" of the FPGA on the NEXYS 4 board. The table also indicates that the "M13" pin is attached to Switch 2 on the board. 
To make an XDC file, follow the instructions in the [[tutorials:making_an_xdc_file]] tutorial. 
Your constraints file should have seven different constraint commands, one for each of the inputs and outputs of your circuit. Remember that it is easier to include the Master XDC File (found on the bar on the left) and uncomment the lines you need rather than making the file yourself.

<color red>Include the text of your XDC file in your laboratory report.</color>

After creating your XDC file, you need to add it to your project. Follow the
[[tutorials:adding_an_xdc_file|]] tutorial to learn how to add this to your project.

=== HDL Synthesis ===

HDL synthesis (also called logic synthesis) is the process of converting your HDL code into an intermediate circuit netlist of gates and logic primitives. Synthesis tools are complex and use a lot of sophisticated algorithms to perform this translation. Follow the [[tutorials:synthesis]] tutorial to run the synthesis tool on your design.

During the synthesis process you may encounter synthesis warnings from the synthesis tool. It is common to receive many warnings especially for large circuits. It is essential that you review the warnings of the synthesis step before proceeding to the implementation step. In most cases these warnings can be ignored but it is essential to review them as subtle warnings in the logic synthesis tool are often are the cause of complex problems later in the design process.  And, like with the comment about simulation you saw earlier, errors that you overlook because you ignore the synthesis warnings may take a LONG time to figure out.  The errors and warnings are there for a reason - don't proceed until you have checked them - it will save you time.

<color red>List the warnings in your synthesis report.</color> State that there were no warnings if none show up. Warnings can be found in the **Messages** tab at the bottom of the screen. They can also be found in the **Reports** tab at the bottom of the screen under **Vivado Synthesis Report**.

<color red>Summarize some of the differences between the schematic you captured earlier and the synthesis schematic.</color> The synthesis schematic is found under **Open Synthesized Design** > **Schematic**, as explained in the [[tutorials:synthesis]] tutorial video.

=== Implementation ===

The Implementation step will map the circuit netlist created in the synthesis step onto specific resources of the FPGA. This involves  placement  of your circuit resources and routing of your logic signals. 
Follow the [[tutorials:implementation]] tutorial to complete the implementation process on your design.

Open the **Project Summary** tab, which should be near the tab for your SystemVerilog file. If you closed the Project Summary earlier, it can be opened with the following icon in the tool bar.

{{ labs:lab_3:project_summary_icon.png }}

Review the **Utilization** box within the Project Summary to determine the size of your design in terms of logic resources. Use the **Post-Implementation** and **Table** tabs.

<color red>Indicate the number of **LUT**s (Look-up Tables) and **I/O** (Input/Output) pins for your design.</color> These are in the **Utilization** column of the table.

**Exercise 4 Pass-off:** Show a TA your xdc file and explain what this file is doing. Then show the TA your synthesized schematic and explain some of the differences between this schematic and the previous one.\\ \\ 


==== Exercise #5: Generate Bitstream and Download to FPGA Board ====

The "Bit File Generation" step will convert your design that has been placed and routed to a binary file that can be downloaded onto the FPGA. 
Follow the [[tutorials:bitgen]] tutorial to generate your bitstream.

Now that you have a bit file, you can configure the FPGA and test your circuit on the board.  Since you have a Vivado project, the process to download a bit file is a bit more streamlined that what you did in the last two labs.  See the second section on the [[tutorials:downloading_bitfile|Downloading Bitfile]] page.

Test all four functions in your circuit on the board to make sure that it works correctly. When you are convinced that your circuit is correct, proceed to the final pass off.

<color red>Submit your final SystemVerilog code using the code submission on Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards).

===== Final Pass Off =====

The following must be shown to a TA to pass off this laboratory:
  * Completed pass-offs for Exercise 2, 3 and 4.
  * The circuit operating correctly on the FPGA board.

<color red>How many hours did you work on the lab?</color>

<color red>Provide any suggestions for improving this lab in the future.</color>

===== Personal Exploration =====

Choose one of the following tasks to do as a personal exploration:
  * Compare and contrast the difference between the circuit you specified in your original SystemVerilog file and the schematic that is generated from your file.  Are there differences?  What is similar and what is different?
  * Add an additional fifth logic function to your SystemVerilog file and synthesize it using the steps described in the laboratory instructions.

<color red>Describe your personal exploration activities</color>

/*

===== Lab Report =====

  * **Header**
    * Class  
    * Lab
    * Name
    * Section
  * **Exercise 2**
    * Schematic screenshot
  * **Exercise 3**
    * Simulation command list
    * Simulation screenshot
  * **Exercise 4**
    * XDC file
    * Synthesis warnings
    * Summary of schematic changes
    * Number of LUTs and I/O pins
  * **Exercise 5**
    * Final Verilog code
  * Personal exploration description
  * Hours spent on lab
  * Feedback


*/
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[[labs:ta:structural_verilog|TA Notes and Feedback]]

[[testDev]]