======Labs======

^ Lab ^ Details ^
| [[archive:winter_2017_labs:lab_0]] | Explanation of lab requirements and processes |
| [[archive:winter_2017_labs:lab_1]] | Introduction to the breadboard and IC chips |
| [[archive:winter_2017_labs:lab_2]] | Introduction to the oscilloscope |
| [[archive:winter_2017_labs:lab_3]] | Introduction to Structural Verilog and Vivado |
| [[archive:winter_2017_labs:lab_4]] | Advanced Structural Verilog |
| [[archive:winter_2017_labs:lab_5]] | Introduction to Dataflow Verilog |
| [[archive:winter_2017_labs:lab_6]] | Advanced Dataflow Verilog |
| [[archive:winter_2017_labs:lab_7]] | Introduction to Behavioral Verilog |
| [[archive:winter_2017_labs:lab_8]] | Advanced Behavioral Verilog |
| [[archive:winter_2017_labs:lab_9]] | Basic state machine design |
| [[archive:winter_2017_labs:lab_10]] | LC3 microprocessor's inner modules |
| [[archive:winter_2017_labs:lab_11]] | Full microprocessor with select instructions |

[[Tutorials]]