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verilog_coding_standards [2019/10/29 16:00] jgoeders |
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| ====== SystemVerilog Coding Standards ====== | ====== SystemVerilog Coding Standards ====== | ||
| **HDL**s (Hardware Description Languages) like SystemVerilog can be difficult to understand. To make SystemVerilog code more readable and maintainable, you are required to follow coding standards. These standards are explained below. Each lab will be graded against this coding standard. | **HDL**s (Hardware Description Languages) like SystemVerilog can be difficult to understand. To make SystemVerilog code more readable and maintainable, you are required to follow coding standards. These standards are explained below. Each lab will be graded against this coding standard. | ||
| + | |||
| + | <color red> | ||
| + | NEW video standard recently added... See below!! | ||
| + | </color> | ||
| + | |||
| + | === Videos === | ||
| + | If you are asked to attach a video to your project, please do it as follows. | ||
| + | |||
| + | There is a about a 150MB limit to the size of video you can upload. On a cellphone at default resolution that is not that long. | ||
| + | You can try to reduce the recording resolution but, at least on an iPhone, you cannot reduce it much. If it is too large, you can try | ||
| + | one of the following: | ||
| + | |||
| + | * Process it using a program to convert it to a 640x480 size video. That should be big enough. | ||
| + | * Upload it to one of Youtube, Dropbox, Google Drive, or Box and enter a link where the TA's can find it instead of actually uploading your video to LearningSuite. | ||
| + | * Find a website that will let you upload and it it will downconvert it for you. CAUTION: these are notorious for installing junk on your computer so be careful if you go this route and use it as a method of last resort. | ||
| + | |||
| + | Of these, Youtube is pretty painless but any of the second group will work. | ||
| + | |||
| === Files=== | === Files=== | ||
| Line 15: | Line 33: | ||
| * | * | ||
| * Author: <Your Name> | * Author: <Your Name> | ||
| - | * Class: <Class, Section, Semester> - ECEN 220, Section 1, Fall 2018 | + | * Class: <Class, Section, Semester> - ECEN 220, Section 1, Winter 2020 |
| * Date: <Date file was created> | * Date: <Date file was created> | ||
| * | * | ||
| Line 35: | Line 53: | ||
| * Are descriptive (''clrTimer'' instead of ''n7''). | * Are descriptive (''clrTimer'' instead of ''n7''). | ||
| * Will have a ''_n'' suffix for active low signals (eg. ''write_n''). | * Will have a ''_n'' suffix for active low signals (eg. ''write_n''). | ||
| - | * Local signal declarations will come just after the module definition and its port declarations. | + | |
| * When signals are declared, they will not use an initializer. For example, this is incorrect: ''logic nextState = 0;''. Rather, signals will be declared as in ''logic nextState;''. | * When signals are declared, they will not use an initializer. For example, this is incorrect: ''logic nextState = 0;''. Rather, signals will be declared as in ''logic nextState;''. | ||
| /*Any initializations you want done to your registers will be done explicitly via the assertion of signals such as 'clrTimer' and the like.*/ | /*Any initializations you want done to your registers will be done explicitly via the assertion of signals such as 'clrTimer' and the like.*/ | ||
| Line 54: | Line 72: | ||
| === Suggested Style=== | === Suggested Style=== | ||
| * The code for the different sub-modules in a module will be grouped together. For example, the statements associated with the timer circuitry will appear together, followed by the statements associated with the bit counter circuitry, followed by the state machine. Each such section of circuitry will have comments delimiting it. | * The code for the different sub-modules in a module will be grouped together. For example, the statements associated with the timer circuitry will appear together, followed by the statements associated with the bit counter circuitry, followed by the state machine. Each such section of circuitry will have comments delimiting it. | ||
| + | * Local signal declarations will come just after the module definition and its port declarations. | ||
| + | * In programming (as well as HDL-based design) there are two common ways of naming signals so that their meaning is obvious. | ||
| + | * One way is called camel case and consists of starting the signal name with a lower case letter and then capitalizing subsequent words as in: clearTimer, resetConfigurationRegisters, or launchMissile. | ||
| + | * The second way is to make everything lower case and use underscores to separate the pieces as in: clear_timer, reset_configuration_registers, and launch_missile. | ||
| + | * Choose one of these two styles, be consistent, and use descriptive signal names. | ||
| + | * Similarly, there are common ways of naming modules and constants. For modules, it is common practice to start their names with a capital letter as in: EventCounter or InitializationRegisters. For constants (sometimes called parameters in SystemVerilog), it is common to make them uppercase as in INITVAL, THRESHOLD, or DATAWIDTH. | ||
| + | * Why would any of this be important? In a large design with literally 100,000's of signals and 1,000's of modules, this will add uniformity to the design to help make the code more readable and maintain-able. | ||
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