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tutorials:viewing_design_elaboration [2018/06/25 11:46] kenmcg SV update |
tutorials:viewing_design_elaboration [2019/07/12 19:20] (current) jgoeders [Refreshing the Schematic] |
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| This will teach you how to view your SystemVerilog code as a schematic. This can be helpful in quickly finding simple errors or double checking that your code matches what you're trying to design. | This will teach you how to view your SystemVerilog code as a schematic. This can be helpful in quickly finding simple errors or double checking that your code matches what you're trying to design. | ||
| - | {{ :tutorials:view_schematic:vivado_view_verilog_as_schematic.mp4| }} | + | {{youtube>ohZC_w5mCUE?rel=0&noborder&1080x700}} |
| - | - First, set the module you want to view as a schematic as your top module. Find the module under **Design Sources**, right click it and click **Set as Top**. (If your module is already set as the top module, this option will be grayed out.) \\ {{ :tutorials:set_as_top_module.png?nolink&200 |}} | + | - First, set the module you want to view as a schematic as your top module. Find the module under **Design Sources**, right click it and click **Set as Top**. (If your module is already set as the top module, this option will be grayed out.) \\ |
| - | - Click **Open Elaborated Design** on the left in the Flow Navigator. \\ {{ :tutorials:view_schematic:open_elaborate_design.png?nolink&200 |}} | + | - Click **Open Elaborated Design** on the left in the Flow Navigator. \\ |
| - | - If this window pops up, click **OK**. \\ {{ :tutorials:view_schematic:elaborate_design_pop_up.png?nolink&300 |}} | + | - If this window pops up, click **OK**. \\ {{ :tutorials:view_schematic:elaborate_design_pop_up.png?nolink&300 |}} |
| - After a short wait, it will display a schematic of your design. | - After a short wait, it will display a schematic of your design. | ||
| - If there are triangles that look like the below image in your schematic, these are not **NOT** gates (there is no inversion bubble on the tip of the triangle). These are called **buffers**, notice that they are labeled with **OBUF** underneath them. A buffer essentially passes its input to its output. You can ignore them for this class, Vivado generates them. \\ {{ :tutorials:view_schematic:buffer_ignore.png?nolink |}} | - If there are triangles that look like the below image in your schematic, these are not **NOT** gates (there is no inversion bubble on the tip of the triangle). These are called **buffers**, notice that they are labeled with **OBUF** underneath them. A buffer essentially passes its input to its output. You can ignore them for this class, Vivado generates them. \\ {{ :tutorials:view_schematic:buffer_ignore.png?nolink |}} | ||
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| If you make changes to your SystemVerilog code after opening the elaborated design, you need to update the schematic. To do so, right click on **Elaborated Design** and click **Reload Design**. | If you make changes to your SystemVerilog code after opening the elaborated design, you need to update the schematic. To do so, right click on **Elaborated Design** and click **Reload Design**. | ||
| - | {{ :tutorials:view_schematic:vivado_refresh_schematic.mp4| }} | + | {{youtube>6lV3Ybhq2z4?rel=0&noborder&1080x700}} |
| A bar near the top of the Vivado window may also appear stating that the elaborated design is out-of-date. Clicking **Reload** on this bar will also successfully refresh the schematic. | A bar near the top of the Vivado window may also appear stating that the elaborated design is out-of-date. Clicking **Reload** on this bar will also successfully refresh the schematic. | ||
