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tutorials:tcl_tutorial [2020/02/05 13:53] nelson [The Basics] |
tutorials:tcl_tutorial [2020/02/05 14:00] (current) nelson [Running your TCL Files] |
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| =====Running your TCL Files===== | =====Running your TCL Files===== | ||
| - | Once you've created your file there is a way to run it using the TCL command line and the file directory but in the writer's opinion that takes more trouble than it's worth. A much more straightforward approach is to copy all of the commands from your TCL file and paste them directly into the TCL command line. Even easier than that, if your TCL file is open in Vivado you can right-click anywhere inside it and the last option will be to run it in the simulator. | + | There are two ways to run a simulation with your TCL files. In either case, you first ned to have a simulation open. Then, do one of the above: |
| + | - Make sure your TCL file is open in Vivado. Right-click anywhere inside it and the last option at the bottom of the menu that pops up will be to run it in the simulator. | ||
| + | - Open your TCL File. Copy its contents and paste them into the TCL command line. | ||
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| + | Obviously, the first options is easier. But, if for some reason you have your commands somewhere else other than in the Vivado editor you can use the second method. | ||
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| + | ===One More Thing About TCL Files=== | ||
| + | Imagine you have opened a simulation and are editing your TCL file. You can edit it repeatedly and re-run it repeatedly using method #1 from above. If your TCL file has a "restart" at the top, it will just restart the simulation, meaning reset the circuit to its initial state and re-simulate it. Thus, you can avoid having to restart the simulation repeatedly as you edit TCL files. | ||
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| + | HOWEVER, if you actually edit your SystemVerilog code then restarting the simulation in this way will not work. You MUST re-compile your new circuit description. This can be done by selected "Re-Launch Simulation" from the "Run" menu in Vivado (the Run menu will only appear if you have a simulation currently running). You can tell it has re-compiled your design when it uses terms like "analyze" and "elaborate" to describe its progress. When in doubt, kill the simulation and re-run it from scratch. | ||
| That is all the information you need to start making your own TCL files. In lab 4, you will cover more features of TCL commands that will make it easier for you to fully simulate your modules. | That is all the information you need to start making your own TCL files. In lab 4, you will cover more features of TCL commands that will make it easier for you to fully simulate your modules. | ||
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