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tutorials:creating_a_new_module [2019/07/12 18:56]
jgoeders [Adding a New SystemVerilog File]
tutorials:creating_a_new_module [2019/07/12 20:05] (current)
jgoeders [Adding a Previously Created Module]
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 ====Adding a Previously Created Module==== ====Adding a Previously Created Module====
  
-{{ :​tutorials:​creating_verilog_module:​vivado_add_external_source.mp4| }}+/* {{ :​tutorials:​creating_verilog_module:​vivado_add_external_source.mp4| }} */
  
-This probably won't be useful in early labs but will be necessary in the later ones. This steps you through adding a source file that you have previously made (in a past lab probably).+This probably won't be useful in early labs but will be necessary in the later ones. This steps you through adding a source file that you have previously made (either ​in a past lab, or downloaded from the course website).
  
   - Go through steps 1 and 2 in the section above.   - Go through steps 1 and 2 in the section above.
   - Instead of clicking Create File, click **Add Files**.   - Instead of clicking Create File, click **Add Files**.
   - Browse to the location of the source file you wish to add.    - Browse to the location of the source file you wish to add. 
-    - If you created the source in Vivado, you'll have to navigate to that project'​s folder, then to the subfolder named **<​project name>​.srcs** then **sources_1** then **new**.+    - If you created the source in Vivado, and saved the file internal to the project, you'll have to navigate to that project'​s folder, then to the subfolder named **<​project name>​.srcs** then **sources_1** then **new**.
   - Make sure the "Copy sources into project"​ checkbox is marked.   - Make sure the "Copy sources into project"​ checkbox is marked.
   - Click **Finish**.   - Click **Finish**.
  
 +/*
 ==== Adding a file using TCL commands ==== ==== Adding a file using TCL commands ====
  
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 </​code>​ </​code>​
  
 +*/
 ---- ----