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testbenches [2020/03/17 08:42] nelson [Writing a Self-Checking Testbench] |
testbenches [2020/03/17 08:58] (current) nelson [Writing a Self-Checking Testbench] |
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| function void checkData(logic expected); | function void checkData(logic expected); | ||
| if (expected != q) begin | if (expected != q) begin | ||
| - | $display("ERROR %t: %d != %d", $time, expected, data_out); | + | $display("ERROR at time %t: got a %d but expected a %d", $time, q, expected); |
| error_count++; | error_count++; | ||
| end | end | ||
| Line 210: | Line 210: | ||
| Also, the list of inputs and expected values could be stored in an array or read from a file. | Also, the list of inputs and expected values could be stored in an array or read from a file. | ||
| - | Then, why require the user to even compute the expected value? Maybe a python script or C program could be written to do that and create the list of inputs and expected output(s) for you. | + | A similar structure could be applied to the construction of a testbench for a sequential circuit. |
| /* | /* | ||
| And, it could go on and on and on. For example, there is a whole object oriented side to SystemVerilog (which can only be used in testbenches) so that advanced test frameworks can be constructed (we teach a graduate course on that topic). So, did you really think they simulate their quad-core Pentium processor designs containing billions of transistors at Intel by typing Tcl scripts in by hand? :-) | And, it could go on and on and on. For example, there is a whole object oriented side to SystemVerilog (which can only be used in testbenches) so that advanced test frameworks can be constructed (we teach a graduate course on that topic). So, did you really think they simulate their quad-core Pentium processor designs containing billions of transistors at Intel by typing Tcl scripts in by hand? :-) | ||
| */ | */ | ||
| - | |||
| - | ==== Self-Checking Testbenches for Sequential Circuits ==== | ||
| - | The above self-checking testbench is pretty straightforward: apply inputs, wait, check outputs. In the final version all 3 of these steps were wrapped into a single task. | ||
| - | |||
| - | For sequential circuits you often want to separate the wait piece out. So, you will need to a bit of a different organization. A recommendation is to have a function wait for a falling clock edge, check correctness based on what happened at the previous rising edge, and then apply new inputs. Then, the main initial block can advance the clock additional cycles as needed between calls to the function. | ||
| - | |||
| - | This is shown below. | ||
