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testbenches [2020/03/17 08:37] nelson [Other Resources To Learn More] |
testbenches [2020/03/17 08:58] (current) nelson [Writing a Self-Checking Testbench] |
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| function void checkData(logic expected); | function void checkData(logic expected); | ||
| if (expected != q) begin | if (expected != q) begin | ||
| - | $display("ERROR %t: %d != %d", $time, expected, data_out); | + | $display("ERROR at time %t: got a %d but expected a %d", $time, q, expected); |
| error_count++; | error_count++; | ||
| end | end | ||
| Line 210: | Line 210: | ||
| Also, the list of inputs and expected values could be stored in an array or read from a file. | Also, the list of inputs and expected values could be stored in an array or read from a file. | ||
| - | Then, why require the user to even compute the expected value? Maybe a python script or C program could be written to do that and create the list of inputs and expected output(s) for you. | + | A similar structure could be applied to the construction of a testbench for a sequential circuit. |
| /* | /* | ||
| And, it could go on and on and on. For example, there is a whole object oriented side to SystemVerilog (which can only be used in testbenches) so that advanced test frameworks can be constructed (we teach a graduate course on that topic). So, did you really think they simulate their quad-core Pentium processor designs containing billions of transistors at Intel by typing Tcl scripts in by hand? :-) | And, it could go on and on and on. For example, there is a whole object oriented side to SystemVerilog (which can only be used in testbenches) so that advanced test frameworks can be constructed (we teach a graduate course on that topic). So, did you really think they simulate their quad-core Pentium processor designs containing billions of transistors at Intel by typing Tcl scripts in by hand? :-) | ||
| */ | */ | ||
| + | |||
| + | |||
| ==== Using $finish ==== | ==== Using $finish ==== | ||
| By default, when you start a simulation in Vivado it will run for a set amount of time (1000ns) and then stop, awaiting further input from you. | By default, when you start a simulation in Vivado it will run for a set amount of time (1000ns) and then stop, awaiting further input from you. | ||
