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resources:vga_drawer [2019/05/13 13:12] jgoeders |
resources:vga_drawer [2019/05/13 13:12] (current) jgoeders |
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| Note: Although the VGA output is 640x480, the bitmap is only 320x240 pixels, because the limited memory on the FPGA would make it difficult to store a full 640x480 image. The ''BitmapToVga'' module automatically scales up the image to the 640x480 resolution before sending it to the display. | Note: Although the VGA output is 640x480, the bitmap is only 320x240 pixels, because the limited memory on the FPGA would make it difficult to store a full 640x480 image. The ''BitmapToVga'' module automatically scales up the image to the 640x480 resolution before sending it to the display. | ||
| - | ^ Module Name = VgaDrawer ^^^^ | + | ^ Module Name = BitmapToVga^^^^ |
| ^ Port Name ^ Direction ^ Width ^ Description ^ | ^ Port Name ^ Direction ^ Width ^ Description ^ | ||
| | clk | Input | 1 | 100 MHz Clock | | | clk | Input | 1 | 100 MHz Clock | | ||
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| ==== Drawing Pixels ==== | ==== Drawing Pixels ==== | ||
| - | The ''VgaDrawer'' module has inputs that let you change the value of the pixels in the bitmap image, allowing you to draw things on the VGA monitor. | + | The ''BitmapToVga'' module has inputs that let you change the value of the pixels in the bitmap image, allowing you to draw things on the VGA monitor. |
| The (x,y) layout of the bitmap is shown below: | The (x,y) layout of the bitmap is shown below: | ||
| Line 47: | Line 47: | ||
| ==== VGA Clock ==== | ==== VGA Clock ==== | ||
| - | The ''VgaDrawer'' requires a 25MHz clock. This is because the 640x480 VGA standard requires that pixels be sent at a rate of ~25MHz. | + | The ''BitmapToVga'' requires a 25MHz clock. This is because the 640x480 VGA standard requires that pixels be sent at a rate of ~25MHz. |
| You have been given the ''clk_generator'' module that uses special circuity on the FPGA (a Phase-Locked Loop (PLL), https://en.wikipedia.org/wiki/Phase-locked_loop) to derive a new clock based on the input 100MHz clock. | You have been given the ''clk_generator'' module that uses special circuity on the FPGA (a Phase-Locked Loop (PLL), https://en.wikipedia.org/wiki/Phase-locked_loop) to derive a new clock based on the input 100MHz clock. | ||
