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resources:rc4 [2019/07/11 21:10] jgoeders |
resources:rc4 [2019/11/01 16:39] (current) jgoeders |
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| ====== RC4 Decryption Module ====== | ====== RC4 Decryption Module ====== | ||
| + | This module provides RC4 encryption/decryption. Like other encryption algorithms, RC4 takes a human-readable message, called the **plaintext**, as well as a secret **key**, and produces an encrypted message of the same length, called the **cyphertext**. In the decryption process, you provide the cyphertext and the same key, and the original plaintext is produced. | ||
| + | You can read about RC4 encryption at [[https://en.wikipedia.org/wiki/RC4]]. RC4 is very simple and can be implemented in about 10-15 lines of software code, that you can find in the //Key-scheduling algorithm (KSA)// and //Pseudo-random generation algorithm (PRGA)// sections at the Wikipedia link. Essentially, RC4 takes a key of any length of bytes, and uses it to create an endless stream of pseudo-random bytes. These bytes are XOR'd with the user message to produce the cyphertext. | ||
| - | <file SystemVerilog decrypt_rc4.sv> | + | As you may be aware, if we XOR a value with another value twice, we get back the original value (''A ^ B ^ B == A''). Thus, if we use the same key to generate the same pseudo-random stream of bytes, and XOR'd them with the cyphertext, we will get back the original plaintext. Using the same key and algorithm for encryption and decryption makes RC4 a **symmetric** encryption algorithm. This means that the provided module can be used to perform either encryption or decryption. |
| + | |||
| + | Assuming one is using the provided module to perform RC4 decryption, the cyphertext is provided to the ''bytes_in'' input, and the key to the ''key'' input. The decryption process begins when the ''enable'' signal is raised, and when completed, the ''done'' output will be high for a single cycle. The resulting plaintext is available from the ''bytes_out'' output, which won't change until you start a new encryption/decryption process (by lower and raising the enable signal). | ||
| + | |||
| + | ^ Module Name = decrypt_rc4 ^^^^ | ||
| + | ^ Parameter ^ Default Value ^ Description ^^ | ||
| + | | BYTES_LEN | 16 | The length of byte stream the encryption engine will process. || | ||
| + | ^ Port Name ^ Direction ^ Width ^ Description ^ | ||
| + | | clk | Input | 1 | 100 MHz Clock | | ||
| + | | reset | Input | 1 | Active-high reset | | ||
| + | | enable| Input | 1 | Set high to start running the decryption. Once started the decryption will continue until finished. You need to lower this signal and then raise it again to start a new decryption process. | | ||
| + | | key | Input | 24 | Encryption key | | ||
| + | | done | Output | 1 | Active-high for one cycle when the encryption/decryption completes| | ||
| + | | bytes_in | Input | BYTES_LEN * 8 | Input bytes (plaintext for encryption, cyphertext for decryption) | | ||
| + | | bytes_out | Output | BYTES_LEN * 8 | Output bytes (cyphertext for encryption, plaintext for decryption) | | ||
| + | |||
| + | Click the link below to download the file. | ||
| + | <file Verilog decrypt_rc4.sv> | ||
| module decrypt_rc4 #( | module decrypt_rc4 #( | ||
| - | parameter MSG_BYTES = 16 | + | parameter BYTES_LEN = 16 |
| ) ( | ) ( | ||
| input wire logic clk, // Clock | input wire logic clk, // Clock | ||
| input wire logic reset, // Active-high reset | input wire logic reset, // Active-high reset | ||
| - | input wire logic start, // Start encryption/decryption | + | input wire logic enable, // Start encryption/decryption |
| input wire logic [23:0] key, // 3 byte key | input wire logic [23:0] key, // 3 byte key | ||
| - | input wire logic [(MSG_BYTES * 8) - 1:0] bytes_in, // byte stream in | + | input wire logic [(BYTES_LEN * 8) - 1:0] bytes_in, // byte stream in |
| - | output logic [(MSG_BYTES * 8) - 1:0] bytes_out, // byte stream out | + | output logic [(BYTES_LEN * 8) - 1:0] bytes_out, // byte stream out |
| output logic done // Active-high done | output logic done // Active-high done | ||
| ); | ); | ||
| Line 82: | Line 101: | ||
| case(cs) | case(cs) | ||
| S_INIT: | S_INIT: | ||
| - | if (start) | + | if (enable) |
| cs <= S_LOOP1; | cs <= S_LOOP1; | ||
| S_LOOP1: | S_LOOP1: | ||
| Line 110: | Line 129: | ||
| S_update_text_out: begin | S_update_text_out: begin | ||
| if (msg_byte_idx == 0) begin | if (msg_byte_idx == 0) begin | ||
| - | cs <= S_INIT; | + | cs <= S_DONE; |
| done <= 1'b1; | done <= 1'b1; | ||
| end else begin | end else begin | ||
| Line 116: | Line 135: | ||
| end | end | ||
| end | end | ||
| + | S_DONE: | ||
| + | if (!enable) | ||
| + | cs <= S_INIT; | ||
| endcase | endcase | ||
| end | end | ||
| Line 141: | Line 163: | ||
| i <= 0; | i <= 0; | ||
| j <= 0; | j <= 0; | ||
| - | msg_byte_idx <= (MSG_BYTES - 1); | + | msg_byte_idx <= (BYTES_LEN - 1); |
| end | end | ||
| S_LOOP3_readSi: begin | S_LOOP3_readSi: begin | ||
