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--- resources:combinational_logic_styles [2019/07/01 10:14]
jgoeders
+++ resources:combinational_logic_styles [2020/02/07 16:22] (current)
nelson
@@ Line 56: / Line 56: @@
 === Dataflow SV ===
-Using assign statement, and the ternary operator:
+Using assign statement, and the ternary operator (also known as the ?: operator):
 <code SystemVerilog>
-assign out = in[2] ? (in[1] ? (in[0] ? 1'b1 : 1'b0)
+assign out =
-                            : (in[0] ? 1'b0 : 1'b1))
+  (in==3’b000)?0:
-                   : (in[1] ? (in[0] ? 1'b0 : 1'b1)
+  (in==3’b001)?1:
-                            : (in[0] ? 1'b1 : 1'b0));
+  (in==3’b010)?1:
+  (in==3’b011)?0:
+  (in==3’b100)?1:
+  (in==3’b101)?0:
+  (in==3’b110)?0:
+;
 </code>

BYU ECEn 220