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| Both sides previous revision Previous revision Next revision | Previous revision | ||
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resources:combinational_logic_styles [2019/06/28 11:15] jgoeders |
resources:combinational_logic_styles [2020/02/07 16:22] (current) nelson |
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| </code> | </code> | ||
| - | Assuming the above SystemVerilog code, there are many different ways to implement the same combinational logic: | + | Assuming the above SystemVerilog code, there are many different ways to implement the same combinational logic. Here are some different examples: |
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| Line 43: | Line 43: | ||
| and(term3, in[2], in_not[1], in_not[0]); | and(term3, in[2], in_not[1], in_not[0]); | ||
| and(term4, in[2], in[1], in[0]); | and(term4, in[2], in[1], in[0]); | ||
| - | or(out, term1, term2, term3, term4) | + | or(out, term1, term2, term3, term4); |
| </code> | </code> | ||
| Line 56: | Line 56: | ||
| === Dataflow SV === | === Dataflow SV === | ||
| - | Using assign statement, and the ternary operator: | + | Using assign statement, and the ternary operator (also known as the ?: operator): |
| <code SystemVerilog> | <code SystemVerilog> | ||
| - | assign out = in[2] ? (in[1] ? (in[0] ? 1'b1 : 1'b0) | + | assign out = |
| - | : (in[0] ? 1'b0 : 1'b1)) | + | (in==3’b000)?0: |
| - | : (in[1] ? (in[0] ? 1'b0 : 1'b1) | + | (in==3’b001)?1: |
| - | : (in[0] ? 1'b1 : 1'b0)); | + | (in==3’b010)?1: |
| + | (in==3’b011)?0: | ||
| + | (in==3’b100)?1: | ||
| + | (in==3’b101)?0: | ||
| + | (in==3’b110)?0: | ||
| + | 1; | ||
| </code> | </code> | ||
