User Tools
Differences
This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision Next revision | Previous revision | ||
|
resources:combinational_logic_styles [2019/06/28 11:12] jgoeders |
resources:combinational_logic_styles [2020/02/07 16:22] (current) nelson |
||
|---|---|---|---|
| Line 18: | Line 18: | ||
| <code SystemVerilog> | <code SystemVerilog> | ||
| - | logic [3:0] in; | + | logic [2:0] in; |
| logic out; | logic out; | ||
| Line 25: | Line 25: | ||
| </code> | </code> | ||
| - | Assuming the above SystemVerilog code, there are many different ways to implement the same combinational logic: | + | Assuming the above SystemVerilog code, there are many different ways to implement the same combinational logic. Here are some different examples: |
| + | |||
| + | ---- | ||
| === Structural SV === | === Structural SV === | ||
| Line 31: | Line 33: | ||
| Sum of Products: | Sum of Products: | ||
| <code SystemVerilog> | <code SystemVerilog> | ||
| - | logic not0, not1, not2; | + | logic [2:0] in_not; |
| - | not(not0, in[0]); | + | not(in_not[0], in[0]); |
| - | not(not1, in[1]); | + | not(in_not[1], in[1]); |
| - | not(not2, in[2]); | + | not(in_not[2], in[2]); |
| - | and(term1, not2, not1, in[0]); | + | and(term1, in_not[2], in_not[1], in[0]); |
| - | and(term1, not2, in[1], not0); | + | and(term2, in_not[2], in[1], in_not[0]); |
| - | and(term1, in[2], not1, not0); | + | and(term3, in[2], in_not[1], in_not[0]); |
| - | and(term1, in[2], in[1], in[0]); | + | and(term4, in[2], in[1], in[0]); |
| - | or(out, term1, term2, term3, term4) | + | or(out, term1, term2, term3, term4); |
| </code> | </code> | ||
| Line 49: | Line 51: | ||
| xor(out, in[2], in[1], in[0]); | xor(out, in[2], in[1], in[0]); | ||
| </code> | </code> | ||
| + | |||
| + | ---- | ||
| === Dataflow SV === | === Dataflow SV === | ||
| - | Using assign statement, and the ternary operator: | + | Using assign statement, and the ternary operator (also known as the ?: operator): |
| <code SystemVerilog> | <code SystemVerilog> | ||
| - | assign out = in[2] ? (in[1] ? (in[0] ? 1'b1 : 1'b0) | + | assign out = |
| - | : (in[0] ? 1'b0 : 1'b1)) | + | (in==3’b000)?0: |
| - | : (in[1] ? (in[0] ? 1'b0 : 1'b1) | + | (in==3’b001)?1: |
| - | : (in[0] ? 1'b1 : 1'b0)); | + | (in==3’b010)?1: |
| + | (in==3’b011)?0: | ||
| + | (in==3’b100)?1: | ||
| + | (in==3’b101)?0: | ||
| + | (in==3’b110)?0: | ||
| + | 1; | ||
| </code> | </code> | ||
| Line 77: | Line 86: | ||
| assign out = (in == 3'd1) || (in == 3'd2) || (in == 3'd4) || (in == 3'd7); | assign out = (in == 3'd1) || (in == 3'd2) || (in == 3'd4) || (in == 3'd7); | ||
| </code> | </code> | ||
| + | ---- | ||
| === Behavioral SV === | === Behavioral SV === | ||
