Differences

This shows you the differences between two versions of the page.

--- resources:combinational_logic_styles [2019/06/28 10:52]
jgoeders
+++ resources:combinational_logic_styles [2020/02/07 16:22] (current)
nelson
@@ Line 18: / Line 18: @@
 <code SystemVerilog>
-logic [3:0] in;
+logic [2:0] in;
 logic       out;
@@ Line 25: / Line 25: @@
 </code>
-Assuming the above SystemVerilog code, there are many different ways to implement the combinational logic:
+Assuming the above SystemVerilog code, there are many different ways to implement the same combinational logic.   Here are some different examples:
+----
 === Structural SV ===
@@ Line 31: / Line 33: @@
 Sum of Products:
 <code SystemVerilog>
-logic not0, not1, not2;
+logic [2:0] in_not;
-not(not0, in[0]);
+not(in_not[0], in[0]);
-not(not1, in[1]);
+not(in_not[1], in[1]);
-not(not2, in[2]);
+not(in_not[2], in[2]);
-and(term1, not2, not1, in[0]);
+and(term1, in_not[2], in_not[1], in[0]);
-and(term1, not2, in[1], not0);
+and(term2, in_not[2], in[1], in_not[0]);
-and(term1, in[2], not1, not0);
+and(term3, in[2], in_not[1], in_not[0]);
-and(term1, in[2], in[1], in[0]);
+and(term4, in[2], in[1], in[0]);
-or(out, term1, term2, term3, term4)
+or(out, term1, term2, term3, term4);
 </code>
@@ Line 49: / Line 51: @@
 xor(out, in[2], in[1], in[0]);
 </code>
+----
 === Dataflow SV ===
-Using the ternary operator:
+Using assign statement, and the ternary operator (also known as the ?: operator):
+<code SystemVerilog>
+assign out =
+  (in==3’b000)?0:
+  (in==3’b001)?1:
+  (in==3’b010)?1:
+  (in==3’b011)?0:
+  (in==3’b100)?1:
+  (in==3’b101)?0:
+  (in==3’b110)?0:
+;
+</code>
+Using assign statement, with sum of products, and dataflow operators :
+<code SystemVerilog>
+assign out = (~in[2] & ~in[1] & in[0]) | (~in[2] & in[1] & ~in[0]) |
+             (in[2] & ~in[1] & ~in[0]) | (in[2] & in[2] & in[0]);
+</code>
+Using assign statement, vectored comparison operators, binary literals:
+<code SystemVerilog>
+assign out = (in == 3'b001) || (in == 3'b010) || (in == 3'b100) || (in == 3'b111);
+</code>
+Using assign statement, vectored comparison operators, decimal literals:
+<code SystemVerilog>
+assign out = (in == 3'd1) || (in == 3'd2) || (in == 3'd4) || (in == 3'd7);
+</code>
+----
+=== Behavioral SV ===
+Using ''always_comb'' block with if statement.
+<code SystemVerilog>
+always_comb begin
+    out = 1'b0;
+    if ((in == 3'b001) || (in == 3'b010) || (in == 3'b100) || (in == 3'b111)) begin
+        out = 1'b1;
+    end else begin
+        // This else isn't necessary because of the default value at the top, but is included here
+        // to show you the syntax.
+        out = 1'b0;
+    end
+end
+</code>
+Using ''always_comb'' block with case statement.
 <code SystemVerilog>
-assign out = in[2] ? (in[1] ? (in[0] ? 1'b1 : 1'b0)
+always_comb begin
-                            : (in[0] ? 1'b0 : 1'b1))
+    out = 1'b0;
-                   : (in[1] ? (in[0] ? 1'b0 : 1'b1)
+    case(in)
-                            : (in[0] ? 1'b1 : 1'b0))
+'b001: out = 1'b1;
+'b010: out = 1'b1;
+'b100:
+            out = 1'b1;
+'b111: begin
+            out = 1'b1;
+        end
+        default: begin
+            // This default isn't necessary because of the default value at the top, but is included here
+            // to show you the syntax.
+            out = 1'b0;
+        end
+    endcase
+end
 </code>
+The example above mixes different formatting of the case statements to show you the variations available.  //Note:// Similar to ''if'' and ''always'' blocks, you will need to include a ''begin'' and ''end'' if your case contains more than one statement.

User Tools

Differences

Page Tools

BYU ECEn 220

Site Tools