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resources:char_drawer [2019/07/11 16:20]
jgoeders
resources:char_drawer [2019/11/01 16:41] (current)
jgoeders
Line 27: Line 27:
  
 ^ Module Name = CharDrawer ^^^^ ^ Module Name = CharDrawer ^^^^
-^ Parameter ^ Description ​^^^ +^ Parameter ​^ Default Value ^ Description ^^ 
-| MAX_CHARS | The length of the string that the module can display. |+| MAX_CHARS ​| 16 |The length of the string that the module can display. ​||
 ^ Port Name ^ Direction ^ Width ^ Description ^ ^ Port Name ^ Direction ^ Width ^ Description ^
 | clk | Input | 1 | 100 MHz Clock | | clk | Input | 1 | 100 MHz Clock |
 | reset | Input | 1 | Active-high reset | | reset | Input | 1 | Active-high reset |
-start | Input | 1 | Active-high, ​start drawing ​the string |+enable| Input | 1 | Raise this signal to start drawing.  The drawing will continue until finished. ​ To draw a new string ​you must lower and then raise this signal. ​|
 | done | Output | 1 | Active-high,​ indicating that the string is done drawing | | done | Output | 1 | Active-high,​ indicating that the string is done drawing |
 | x_in | Input | 9 | Top-left x-coordinate of drawing region | | x_in | Input | 9 | Top-left x-coordinate of drawing region |
Line 40: Line 40:
 | y_out| Output | 8 | y-Coordinate of pixel to draw | | y_out| Output | 8 | y-Coordinate of pixel to draw |
  
 +Click the link below to download the CharDrawer.sv file.
  
-<​file ​SystemVerilog ​CharDrawer.sv>​+<​file ​Verilog ​CharDrawer.sv>​
 module CharDrawer # ( module CharDrawer # (
     parameter MAX_CHARS = 16     parameter MAX_CHARS = 16
Line 47: Line 48:
     input wire logic                            clk,        // Clock     input wire logic                            clk,        // Clock
     input wire logic                            reset, ​     // Active-high reset     input wire logic                            reset, ​     // Active-high reset
-    input wire logic                            ​start     // Start drawing+    input wire logic                            ​enable    ​// Start drawing
     output logic                                done,       // Done drawing     output logic                                done,       // Done drawing
     input wire logic    [8:0]                   ​x_in, ​      // Top-left (x,y)     input wire logic    [8:0]                   ​x_in, ​      // Top-left (x,y)
Line 90: Line 91:
  
 // State Machine ​ // State Machine ​
-typedef enum {S_INIT, S_NEXT_CHAR,​ S_READ_ROW, S_SAVE_ROW, S_DRAW_ROW} StateType;+typedef enum {S_INIT, S_NEXT_CHAR,​ S_READ_ROW, S_SAVE_ROW, S_DRAW_ROW, S_DONE} StateType;
 StateType cs; StateType cs;
  
Line 112: Line 113:
         case (cs)         case (cs)
             S_INIT:             S_INIT:
-                if (start)+                if (enable)
                     cs <= S_NEXT_CHAR; ​       ​                     cs <= S_NEXT_CHAR; ​       ​
             S_NEXT_CHAR:​             S_NEXT_CHAR:​
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                     cs <= S_READ_ROW;                     cs <= S_READ_ROW;
                 else if (char_idx == 0)                 else if (char_idx == 0)
-                    cs <= S_INIT;        ​+                    cs <= S_DONE;        ​
             S_READ_ROW:             S_READ_ROW:
                 cs <= S_SAVE_ROW;                 cs <= S_SAVE_ROW;
Line 127: Line 128:
                     if (row_done) begin                     if (row_done) begin
                         if (char_idx == 0) begin                         if (char_idx == 0) begin
-                            cs <= S_INIT;+                            cs <= S_DONE;
                         end else begin                         end else begin
                             cs <= S_NEXT_CHAR;​                             cs <= S_NEXT_CHAR;​
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                 end                 end
             end             end
 +            S_DONE:
 +             if (!enable)
 +                cs <= S_INIT;
         endcase         endcase
     end     end