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labs:w20_uart_rx [2020/04/13 11:18] nelson [Exercise #3 - Loop-Back Simulation Test] |
labs:w20_uart_rx [2020/04/13 11:30] (current) nelson [Exercise #3 - Loop-Back Simulation Test] |
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| ==== Exercise #3 - Loop-Back Simulation Test ==== | ==== Exercise #3 - Loop-Back Simulation Test ==== | ||
| - | After simulating your receiver module and verifying it operates, begin a new top-level module with the following ports: | + | In this exercise you are going to simulate a transmitter/receiver pair as shown in the figure below. |
| + | |||
| + | {{:labs:lab_11:img_0065.jpg?900|}} | ||
| + | |||
| + | Here, there is a transmitter (with its host) located in Boston that is going to transmit bytes to a receiver (with its host) located in San Francisco. But, to mimic that you are going to put your transmitter from Lab 10 and your receiver from Lab 11 into the same top module. | ||
| + | |||
| + | Your Tcl file will act as //both// the Boston host and the San Francisco host. That is, it will handshake with the transmitter to send a byte like in Lab 10. But, that byte will be transmitted to your receiver which will then receive it like in this lab and so your Tcl file will also have do handhshaking with the receiver to acknowledge that. | ||
| + | |||
| + | The actual serial data transmission, rather than actually traveling from Boston to San Franciso will travel a few nanometers on a wire inside the FPGA from the transmitter's output to the receiver's input. | ||
| + | |||
| + | Make a new top-level module with the following ports: | ||
| ^ Module Name = uart_top ^^^^ | ^ Module Name = uart_top ^^^^ | ||
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| | Received | Input | 1 | Receive handshake: host acknowledge receipt of character | | | Received | Input | 1 | Receive handshake: host acknowledge receipt of character | | ||
| | parityErr | Output | 1 | Parity error signal | | | parityErr | Output | 1 | Parity error signal | | ||
| + | | serData | Output | 1 | The serial signal between xmit and rcv blocks. You are bringing it out as an output so you can easily see it in simulation. | | ||
| + | |||
| + | Note that you are NOT going to map these I/O signals to board-level switches and led's. You are simply going to simulate this top level module. | ||
| Inside this module, instance both your tx and rx modules. Then, connect the serial out | Inside this module, instance both your tx and rx modules. Then, connect the serial out | ||
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| Now, write a Tcl file and do the simulation of your complete | Now, write a Tcl file and do the simulation of your complete | ||
| circuit. A complete transmission consists of applying txData and the | circuit. A complete transmission consists of applying txData and the | ||
| - | send signal and waiting for a sent signal to be returned and then | + | Send signal and waiting for a Sent signal to be returned and then |
| - | lowering the send signal. That handles the transmit handshaking. | + | lowering the Send signal. That handles the transmit handshaking. |
| But, there will also be receive handshaking once the byte has been | But, there will also be receive handshaking once the byte has been | ||
| received by the receiver. That is, once a byte has been received your | received by the receiver. That is, once a byte has been received your | ||
| - | receiver should raise the Receive signal. Your Tcl file can then | + | receiver will raise the Receive signal. Your Tcl file can then |
| respond by raising the Received signal, waiting until the Receive | respond by raising the Received signal, waiting until the Receive | ||
| signal has been lowered, and then lowering the Received signal. | signal has been lowered, and then lowering the Received signal. | ||
| + | |||
| + | Your simulation should show that whatever byte was requested to be transmitted by your transmitter is what | ||
| + | was received by your receiver. | ||
| **Exercise 3 Pass-off:** <del>Show a TA your top level module and | **Exercise 3 Pass-off:** <del>Show a TA your top level module and | ||
