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labs:uart_tx [2020/03/19 10:21] nelson [Exercise #3 - Top-Level TX Circuit] |
labs:uart_tx [2020/04/30 09:46] (current) nelson old revision restored (2020/03/02 17:32) |
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| - | <color red> | ||
| - | ### UNDER CONSTRUCTION ### \\ \\ | ||
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| - | NOTE: changes have been made to the lab below. Items you no longer are required to do are shown with a <del>strikethrough</del>. | ||
| - | </color> | ||
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| - | |||
| ====== UART Transmitter ====== | ====== UART Transmitter ====== | ||
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| ^ Module Name = tx ^^^^ | ^ Module Name = tx ^^^^ | ||
| + | ^ Parameter ^ Type (Default) ^^ Function ^ | ||
| ^ Port Name ^ Direction ^ Width ^ Function ^ | ^ Port Name ^ Direction ^ Width ^ Function ^ | ||
| | clk | Input | 1 | 100 MHz System Clock | | | clk | Input | 1 | 100 MHz System Clock | | ||
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| * Check that both of your timers are operating correctly; that they reset and increment in the correct conditions. | * Check that both of your timers are operating correctly; that they reset and increment in the correct conditions. | ||
| - | **Exercise 1 Pass-off:** <del>Show a TA your waveform</del> Share your waveform with the TA in Zoom and discuss how the waveform demonstrates the above points. | + | **Exercise 1 Pass-off:** Show a TA your waveform and discuss how the waveform demonstrates the above points. |
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| </file> | </file> | ||
| - | Look over the top-level file. You will see that it uses your debounce circuit from a previous lab, which ensures that when you hit the send button, only a single character is sent. The seven segment controller displays the current value of the switches to help quickly determine the hexadecimal value and compare it to an ASCII table. | + | Look over the top-level file. You will see that it uses your debouce circuit from a previous lab, which ensures that when you hit the send button, only a single character is sent. The seven segment controller displays the current value of the switches to help quickly determine the hexadecimal value and compare it to an ASCII table. |
| /* | /* | ||
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| * Using another debouncer instance, debounce the 'btnd' input to create the 'reset' signal. | * Using another debouncer instance, debounce the 'btnd' input to create the 'reset' signal. | ||
| - | **Exercise 3 Pass-off:** Show a TA your top level module and explain why we need to debounce the button inputs. | + | **Exercise 3 Pass-off:** Show a TA your top level module and explain why we need to debounce the button inputs.\\ \\ |
| - | \\ \\ | + | |
| */ | */ | ||
| - | ** Exercise 3 Pass-off:** Create a Tcl file and show a single reset of the circuit followed by successful transmission of the letter 'Y'. | + | Before synthesizing your design, you will need to create an .xdc file that contains the pin locations of each port in your design. Most of the pins used in this design are the same as pins used in previous designs (buttons, switches, seven-segment display, etc.). However, you will be using a new FPGA pin to connect to the UART/USB transciever and the debug port. |
| - | + | ||
| - | <color red>Document that it was successful via one or more screen shots of the waveforms. If the simulation was so long that you cannot see sufficient detail you may take multiple screen shots of the important times and append them together into one PDF file. </color> | + | |
| - | + | ||
| - | Then, before synthesizing your design, you will need to create an .xdc file that contains the pin locations of each port in your design. Most of the pins used in this design are the same as pins used in previous designs (buttons, switches, seven-segment display, etc.). However, you will be using a new FPGA pin to connect to the UART/USB transciever and the debug port. | + | |
| The following example code demonstrates how these I/O pins can be attached to your top-level FPGA pins: | The following example code demonstrates how these I/O pins can be attached to your top-level FPGA pins: | ||
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| </code> | </code> | ||
| - | After completing your .xdc file, proceed to <del>generate your bitstream</del> do synthesis and implementation. | + | After completing your .xdc file, proceed to generate your bitstream. |
| - | + | ||
| - | <color red>Attached your synthesis and implementation reports. | + | |
| - | Then, provide a summary of your synthesis and implementation warnings</color>. | + | <color red>Provide a summary of your synthesis warnings</color>. |
| **Exercise 3 Pass-off:** There is no pass-off for this exercise.\\ \\ | **Exercise 3 Pass-off:** There is no pass-off for this exercise.\\ \\ | ||
