User Tools
Differences
This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision Next revision | Previous revision | ||
|
labs:uart_tx [2019/11/08 16:17] jgoeders [Exercise #3 - Top-Level TX Circuit] |
labs:uart_tx [2020/04/30 09:46] (current) nelson old revision restored (2020/03/02 17:32) |
||
|---|---|---|---|
| Line 63: | Line 63: | ||
| ** FSM ** | ** FSM ** | ||
| - | Create the FSM as outlined in Figure 28.12 . | + | Create the FSM as outlined in the following figure. Note, this is slightly different that the figure in the textbook, which as a small error in the BITS state. |
| + | |||
| + | {{ :labs:uart_tx:uart_tx_sm.png?600 |}} | ||
| Line 77: | Line 79: | ||
| # Reset design | # Reset design | ||
| add_force Reset 1 | add_force Reset 1 | ||
| + | add_force Send 0 | ||
| run 10ns | run 10ns | ||
| add_force Reset 0 | add_force Reset 0 | ||
| Line 125: | Line 128: | ||
| ==== Exercise #3 - Top-Level TX Circuit ==== | ==== Exercise #3 - Top-Level TX Circuit ==== | ||
| - | After simulating your module and verifying it operates, download the following top-level module: | + | After simulating your module and verifying it operates, download the following top-level module (just click the link below to download the file, then add it to your project.): |
| <file Verilog tx_top.sv> | <file Verilog tx_top.sv> | ||
| Line 151: | Line 154: | ||
| logic reset; | logic reset; | ||
| assign reset = ~CPU_RESETN; | assign reset = ~CPU_RESETN; | ||
| + | assign tx_debug = tx_out; | ||
| logic btnc_r; | logic btnc_r; | ||
| Line 196: | Line 200: | ||
| </file> | </file> | ||
| + | Look over the top-level file. You will see that it uses your debouce circuit from a previous lab, which ensures that when you hit the send button, only a single character is sent. The seven segment controller displays the current value of the switches to help quickly determine the hexadecimal value and compare it to an ASCII table. | ||
| + | |||
| + | /* | ||
| begin a new top-level module with the following ports: | begin a new top-level module with the following ports: | ||
| Line 231: | Line 238: | ||
| **Exercise 3 Pass-off:** Show a TA your top level module and explain why we need to debounce the button inputs.\\ \\ | **Exercise 3 Pass-off:** Show a TA your top level module and explain why we need to debounce the button inputs.\\ \\ | ||
| - | ==== Exercise #4 - Implementation ==== | + | */ |
| Before synthesizing your design, you will need to create an .xdc file that contains the pin locations of each port in your design. Most of the pins used in this design are the same as pins used in previous designs (buttons, switches, seven-segment display, etc.). However, you will be using a new FPGA pin to connect to the UART/USB transciever and the debug port. | Before synthesizing your design, you will need to create an .xdc file that contains the pin locations of each port in your design. Most of the pins used in this design are the same as pins used in previous designs (buttons, switches, seven-segment display, etc.). However, you will be using a new FPGA pin to connect to the UART/USB transciever and the debug port. | ||
| Line 241: | Line 248: | ||
| </code> | </code> | ||
| - | After completing your .xdc file, proceed with the synthesis of your design. | + | After completing your .xdc file, proceed to generate your bitstream. |
| <color red>Provide a summary of your synthesis warnings</color>. | <color red>Provide a summary of your synthesis warnings</color>. | ||
| - | After successfully synthesizing your design, proceed with the implementation and bitstream generation of your design. | + | **Exercise 3 Pass-off:** There is no pass-off for this exercise.\\ \\ |
| - | <color red>Indicate the number of Look-up Tables (LUT) and Input/Output (I/O) pins for your design.</color> | + | |
| - | **Exercise 4 Pass-off:** There is no pass-off for this exercise.\\ \\ | ||
| - | + | ==== Exercise #4 - Download and Putty ==== | |
| - | ==== Exercise #5 - Download and Putty ==== | + | |
| Once the bitstream has been generated, download your bitstream to the FPGA. To test the transmitter, you will need to run a program called "PuTTY" that is installed on your computer. Follow the [[tutorials:putty|PuTTY tutorial to set it up.]] | Once the bitstream has been generated, download your bitstream to the FPGA. To test the transmitter, you will need to run a program called "PuTTY" that is installed on your computer. Follow the [[tutorials:putty|PuTTY tutorial to set it up.]] | ||
| Line 266: | Line 270: | ||
| ===== Final Pass Off ===== | ===== Final Pass Off ===== | ||
| - | To pass off this laboratory, demonstrate to the TA the following: | + | To pass off this laboratory, demonstrate to the TA your working top-level transmitter circuit (the TA will test your transmitter with several characters). |
| - | * Pass-offs for Exercises 1, 2, and 3 | + | |
| - | * Your working top-level transmitter circuit (the TA will test your transmitter with several characters) | + | |
| <color red>How many hours did you work on the lab?</color> | <color red>How many hours did you work on the lab?</color> | ||
| Line 276: | Line 278: | ||
| <color red>Submit your SystemVerilog modules using the code submission on Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). | <color red>Submit your SystemVerilog modules using the code submission on Learning Suite.</color> (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). | ||
| ===== Personal Exploration ===== | ===== Personal Exploration ===== | ||
| + | |||
| + | |||
| + | <color #ed1c24>(The Personal Exploration is optional for this lab)</color> | ||
| Here are some ideas for personal exploration in this laboratory: | Here are some ideas for personal exploration in this laboratory: | ||
| Line 283: | Line 288: | ||
| * Hook up the tx debug signal to the oscilliscope and view the transfer of an 8-bit character. | * Hook up the tx debug signal to the oscilliscope and view the transfer of an 8-bit character. | ||
| - | <color red>Describe your personal exploration activities</color> | ||
