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labs:uart_tx [2019/11/08 15:05]
jgoeders [Exercise #2 - Simulation] 		labs:uart_tx [2020/04/30 09:46] (current)
nelson old revision restored (2020/03/02 17:32)
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 <color red>What is the maximum number of 8-bit ASCII characters that can be transmitted per second using your transmitter at a baud rate of 19,​200?</​color>​ (make sure you consider the presence of the start bit, parity bit, and stop bit). <color red>What is the maximum number of 8-bit ASCII characters that can be transmitted per second using your transmitter at a baud rate of 19,​200?</​color>​ (make sure you consider the presence of the start bit, parity bit, and stop bit).
  
 +----
 ===== Exercises ===== ===== Exercises =====
  
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   * The size of the counter (in bits) is based on the baud rate and your system'​s 100MHz clock rate. The counter must have enough bits to represent the largest count value as determined by your calculations above.   * The size of the counter (in bits) is based on the baud rate and your system'​s 100MHz clock rate. The counter must have enough bits to represent the largest count value as determined by your calculations above.
  
-The counter has an output signal that indicates when the counter has reached the last clock cycle of the baud period ('​timerDone'​ in the system diagram). This signal is used as an input in the FSM.+The counter has an output signal that indicates when the counter has reached the last clock cycle of the baud period ('​timerDone'​ in the system diagram). This signal is used as an input in the FSM.  When the timer reaches this point, it must roll over to 0; the state machine design relies upon this. 
  
 ** Parity Generator ** ** Parity Generator **
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 ** FSM ** ** FSM **
  
-Create the FSM as outlined in Figure 28.12 .+Create the FSM as outlined in the following figure.  Note, this is slightly different that the figure in the textbook, which as a small error in the BITS state.
  
-**Exercise 1 Pass-off:** Show a TA your ''​tx''​ module. Your module must include all of the elements listed above and must use the ''​Reset''​ signal to reset your state machine.\\ \\+{{ :labs:​uart_tx:​uart_tx_sm.png?600 |}}
  
  
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 # Reset design # Reset design
 add_force Reset 1 add_force Reset 1
 +add_force Send 0
 run 10ns run 10ns
 add_force Reset 0 add_force Reset 0
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 ---- ----
  
-**Exercise ​1 Pass-off:** Show a TA your tcl file and your testbench output. Your tcl file must meet the listed requirements.\\ \\ +==== Exercise ​#2 - Testbench Validation ====
- +
-After creating your tx module create a TCL simulation file to demonstrate the following operation of your transmitter:​ +
-  - Allow your module to operate in the IDLE state for ~100 us +
-  - Transmit a single 8-bit value +
- +
-<color red>​Include a copy of your TCL file in your lab report</​color>​+
  
 When it looks like your tx module is working properly use the following testbench file to test it.  When it looks like your tx module is working properly use the following testbench file to test it. 
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 <color red>​Include a copy of the simulation console in your laboratory report when your simulation passes the testbench with no errors</​color>​ <color red>​Include a copy of the simulation console in your laboratory report when your simulation passes the testbench with no errors</​color>​
  
 +**Exercise 2 Pass-off:** You don't need a TA to pass of this exercise, but __make sure the testbench is working before moving on__. 
  
 +----
  
-**Exercise ​2 Pass-off:** Show a TA your tcl file and your testbench output. Your tcl file must meet the listed requirements.\\ \\+==== Exercise ​#3 - Top-Level TX Circuit ====
  
 +After simulating your module and verifying it operates, download the following top-level module (just click the link below to download the file, then add it to your project.):
  
-==== Exercise #3 - Top-Level TX Circuit ====+<file Verilog tx_top.sv>​ 
 +//////////////////////////////////////////////////////////////////////////////////​ 
 +// 
 +//  Filename: tx_top.sv 
 +// 
 +//  Author: Jeff Goeders 
 +//   
 +//  Description:​ UART Transmitter top-level design 
 +// 
 +//      
 +//////////////////////////////////////////////////////////////////////////////////​ 
 + 
 +module tx_top( 
 +    input wire logic            clk,  
 +    input wire logic            CPU_RESETN,​ 
 +    input wire logic    [7:0]   sw,  
 +    input wire logic            btnc,  
 +    output logic        [7:0]   ​anode,​  
 +    output logic        [7:0]   ​segment,​  
 +    output logic                tx_out,  
 +    output logic                tx_debug);​ 
 + 
 +    logic reset; 
 +    assign reset = ~CPU_RESETN;​ 
 +    assign tx_debug ​= tx_out; 
 + 
 +    logic   ​btnc_r;​ 
 +    logic   ​btnc_r2;​ 
 +    logic   ​send_character;​ 
 +     
 +    // Button synchronizaer 
 +    always_ff@(posedge clk) 
 +    begin 
 +       ​btnc_r <= btnc; 
 +       ​btnc_r2 <= btnc_r; 
 +    end 
 + 
 +    // Debounce the start button 
 +    debounce debounce_inst( 
 +        .clk(clk),​ 
 +        .reset(reset),​ 
 +        .noisy(btnc_r2),​ 
 +        .debounced(send_character) 
 +    ); 
 +     
 +    // Transmitter 
 +    tx tx_inst( 
 +        .clk    (clk),  
 +        .Reset ​ (reset), 
 +        .Send   ​(send_character),​ 
 +        .Din    (sw), 
 +        .Sent   (), 
 +        .Sout   ​(tx_out) 
 +    ); 
 +         
 +    // Seven Segment Display 
 +    SevenSegmentControl SSC ( 
 +        .clk(clk),​ 
 +        .reset(reset),​ 
 +        .dataIn({24'​h0,​ sw}), 
 +        .digitDisplay(8'​h03),​ 
 +        .digitPoint(8'​h00),​  
 +        .anode(anode),​ 
 +        .segment(segment) 
 +    ); 
 + 
 +     
 +endmodule 
 +</​file>​ 
 + 
 +Look over the top-level file.  You will see that it uses your debouce circuit from a previous lab, which ensures that when you hit the send button, only a single character is sent.  The seven segment controller displays the current value of the switches to help quickly determine the hexadecimal value and compare it to an ASCII table.
  
-After simulating your module and verifying it operates, ​begin a new top-level module with the following ports:+/* 
 +begin a new top-level module with the following ports:
  
 ^ Module Name = tx_top ^^^^ ^ Module Name = tx_top ^^^^
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 **Exercise 3 Pass-off:** Show a TA your top level module and explain why we need to debounce the button inputs.\\ \\ **Exercise 3 Pass-off:** Show a TA your top level module and explain why we need to debounce the button inputs.\\ \\
  
-==== Exercise #4 - Implementation ====+*/
  
 Before synthesizing your design, you will need to create an .xdc file that contains the pin locations of each port in your design. Most of the pins used in this design are the same as pins used in previous designs (buttons, switches, seven-segment display, etc.). However, you will be using a new FPGA pin to connect to the UART/USB transciever and the debug port. Before synthesizing your design, you will need to create an .xdc file that contains the pin locations of each port in your design. Most of the pins used in this design are the same as pins used in previous designs (buttons, switches, seven-segment display, etc.). However, you will be using a new FPGA pin to connect to the UART/USB transciever and the debug port.
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 </​code>​ </​code>​
  
-After completing your .xdc file, proceed ​with the synthesis of your design.+After completing your .xdc file, proceed ​to generate ​your bitstream.
  
 <color red>​Provide a summary of your synthesis warnings</​color>​. <color red>​Provide a summary of your synthesis warnings</​color>​.
  
-After successfully synthesizing your design, proceed with the implementation and bitstream generation of your design.  +**Exercise 3 Pass-off:** There is no pass-off for this exercise.\\ \\
-<color red>​Indicate the number of Look-up Tables (LUT) and Input/​Output (I/O) pins for your design.</​color>​+
  
-**Exercise 4 Pass-off:** There is no pass-off for this exercise.\\ \\ 
  
- +==== Exercise #4 - Download and Putty ====
-==== Exercise #5 - Download and Putty ====+
  
 Once the bitstream has been generated, download your bitstream to the FPGA. To test the transmitter,​ you will need to run a program called "​PuTTY"​ that is installed on your computer. Follow the [[tutorials:​putty|PuTTY tutorial to set it up.]] Once the bitstream has been generated, download your bitstream to the FPGA. To test the transmitter,​ you will need to run a program called "​PuTTY"​ that is installed on your computer. Follow the [[tutorials:​putty|PuTTY tutorial to set it up.]]
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 ===== Final Pass Off ===== ===== Final Pass Off =====
  
-To pass off this laboratory, demonstrate to the TA the following:​ +To pass off this laboratory, demonstrate to the TA your working top-level transmitter circuit (the TA will test your transmitter with several characters).
-  * Pass-offs for Exercises 1, 2, and 3 +
-  * Your working top-level transmitter circuit (the TA will test your transmitter with several characters)+
  
 <color red>How many hours did you work on the lab?</​color>​ <color red>How many hours did you work on the lab?</​color>​
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 <color red>​Submit your SystemVerilog modules using the code submission on Learning Suite.</​color>​ (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards). <color red>​Submit your SystemVerilog modules using the code submission on Learning Suite.</​color>​ (Make sure your SystemVerilog conforms to the lab SystemVerilog coding standards).
 ===== Personal Exploration ===== ===== Personal Exploration =====
 +
 +
 +<color #​ed1c24>​(The Personal Exploration is optional for this lab)</​color>​
  
 Here are some ideas for personal exploration in this laboratory: Here are some ideas for personal exploration in this laboratory:
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   * Hook up the tx debug signal to the oscilliscope and view the transfer of an 8-bit character.   * Hook up the tx debug signal to the oscilliscope and view the transfer of an 8-bit character.
  
-<color red>​Describe your personal exploration activities</​color>​ 
  
  

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