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labs:uart_rx [2019/04/02 21:40] nelson [Exercise #2 - Simulation] |
labs:uart_rx [2019/04/09 11:47] (current) djlee |
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| ====== UART Receiver ====== | ====== UART Receiver ====== | ||
| - | In this laboratory you will create an asynchronous serial receiver that will allow you to receive characters from your computer and onto the NEXYS4 board. Your design will closely follow last week's serial transmitter. That is, you will have handshaking with the receiver (but the signals are called Receive and Received). And, the receiver has similar components - a state machine, a bit counter, and a timer. A number of the details are different but it will have a similar organization. | + | In this laboratory you will create an asynchronous serial receiver that will allow you to send characters from your computer to the NEXYS4 board. Your design will closely follow last week's serial transmitter. That is, you will have handshaking with the receiver (but the signals are called Receive and Received). And, the receiver has similar components - a state machine, a bit counter, and a timer. A number of the details are different but it will have a similar organization. |
| ===== Learning Outcomes ===== | ===== Learning Outcomes ===== | ||
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| ===Finite State Machine=== | ===Finite State Machine=== | ||
| - | You get to design this yourself from scratch. However, we suggest you pattern it somewhat after the transmitter state machine. Note that you have to have your timer get you over into the middle of each bit period and so your timer may have additional output signals. And, your state machine will need to be designed to control when the shift register shifts so that you collect the 8 data bits and parity bits. Finally, your state machine will need to handshake using hte Receive and Received signals at the end of each byte reception. You may safely assume that a new byte will not start to arrive on the Sin signal before the Receive/Received handshake has completed. You can simulate that way and that will surely be the case when you hook everything up in hardware. | + | You get to design this yourself from scratch. However, we suggest you pattern it somewhat after the transmitter state machine. Note that you have to have your timer get you over into the middle of each bit period and so your timer may have additional output signals. And, your state machine will need to be designed to control when the shift register shifts so that you collect the 8 data bits and parity bits. Finally, your state machine will need to handshake using the Receive and Received signals at the end of each byte reception. You may safely assume that a new byte will not start to arrive on the Sin signal before the Receive/Received handshake has completed. You can simulate that way and that will surely be the case when you hook everything up in hardware. |
| + | **Exercise 1 Pass-off:** Show a TA a state graph of your state machine. Show how each of the components listed above are implemented in your rx module.\\ \\ | ||
| ==== Exercise #2 - Simulation ==== | ==== Exercise #2 - Simulation ==== | ||
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| <color red>Include your 'rx' SystemVerilog module in your report</color> | <color red>Include your 'rx' SystemVerilog module in your report</color> | ||
| + | |||
| + | **Exercise 2 Pass-off:** Show a TA your tcl script and your testbench output.\\ \\ | ||
| ==== Exercise #3 - Top-Level Circuit ==== | ==== Exercise #3 - Top-Level Circuit ==== | ||
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| | sw | Input | 8 | Slide switches to specify character to send | | | sw | Input | 8 | Slide switches to specify character to send | | ||
| | btnc | Input | 1 | Send character control signal | | | btnc | Input | 1 | Send character control signal | | ||
| + | | btnd | Input | 1 | Reset signal | | ||
| | rx_in | Input | 1 | Receive signal | | | rx_in | Input | 1 | Receive signal | | ||
| | tx_out | Output | 1 | Transmit signal | | | tx_out | Output | 1 | Transmit signal | | ||
| Line 86: | Line 90: | ||
| * Connect the tx_out output of your tx module to your top-level tx_out output | * Connect the tx_out output of your tx module to your top-level tx_out output | ||
| * Connect the tx_out output of your tx module to the top_level tx_debug output | * Connect the tx_out output of your tx module to the top_level tx_debug output | ||
| - | * Assign the value '0' to the “odd” parity input (for even parity) | + | * Connect an unused signal to the 'Sent' signal of your tx module ('Sent' will not be used in this circuit) |
| - | * Connect an unused signal to the 'busy' signal of your tx module (busy will not be used in this circuit) | + | * Connect the 8 switches to the 'Din' input of your tx module |
| - | * Connect the 8 switches to the 'din' input of your tx module | + | |
| * Connect the top-level clock to the clk input of your tx module | * Connect the top-level clock to the clk input of your tx module | ||
| - | * Drive the tx "send" signal with the same circuit you used in the top-level of your previous lab (attach to btnc, use a synchronizer and debouncer). | + | * Drive the tx "Send" signal with the same circuit you used in the top-level of your previous lab (attach to btnc, use a synchronizer and debouncer). |
| + | * Drive the tx "Reset" signal the same way (attach to btnd, use a synchronizer and debouncer). | ||
| After instancing your tx circuit, instance your rx circuit and connect it to your rx module. | After instancing your tx circuit, instance your rx circuit and connect it to your rx module. | ||
| The rx_error output port at the top level is the parityErr on your rx module and it should be attached to LED[0] on the board. | The rx_error output port at the top level is the parityErr on your rx module and it should be attached to LED[0] on the board. | ||
| - | What to do with the Receive and Received handshaking signals? there is nothing on the board that can acknowledge each byte received. So, in your top level design create a signal called rxHandshake and use it to connect the Receive pin with the Received pin on your rx module. Now, when your rx module says it has a byte read (Receive=1) that will go right back in as Received to complete the handshake. | + | What to do with the Receive and Received handshaking signals? There is nothing on the board that can acknowledge each byte received. So, in your top level design create a signal called rxHandshake and use it to connect the Receive pin with the Received pin on your rx module. Now, when your rx module says it has a byte read (Receive=1) that will go right back in as Received to complete the handshake. |
| Instance your seven segment display controller and connect the inputs to your controller as follows: | Instance your seven segment display controller and connect the inputs to your controller as follows: | ||
| * Attach the 8 switches to the lower 8-bits of the data in of the seven-segment controller (bottom two digits) | * Attach the 8 switches to the lower 8-bits of the data in of the seven-segment controller (bottom two digits) | ||
| - | * Attach the 8-bit signal "rx_data" to bits 23-16 of the data going to the seven segment controller (digits 5 and 4) | + | * Attach the 8-bit signal "rx_in" to bits 23-16 of the data going to the seven segment controller (digits 5 and 4) |
| * Only display the bottom two digits and digits 5 and 4 of the seven segment display | * Only display the bottom two digits and digits 5 and 4 of the seven segment display | ||
| * Do not use any of the digit points | * Do not use any of the digit points | ||
| * Attach the anode and segment signals of the controller to the top-level outputs of the top-level module | * Attach the anode and segment signals of the controller to the top-level outputs of the top-level module | ||
| + | |||
| + | The following diagram illustrates the interconnections of different modules. | ||
| + | |||
| + | {{ :labs:UART_tx_rx.png |}} | ||
| <color red>Include a copy of your top-level module in your laboratory report</color> | <color red>Include a copy of your top-level module in your laboratory report</color> | ||
| + | |||
| + | **Exercise 3 Pass-off:** Show a TA your top level module and explain how we will know when the rx module has received a byte.\\ \\ | ||
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| <color red>Indicate the number of Look-up Tables (LUT) and Input/Output (I/O) pins for your design.</color> | <color red>Indicate the number of Look-up Tables (LUT) and Input/Output (I/O) pins for your design.</color> | ||
| + | **Exercise 4 Pass-off:** There is no pass-off for this exercise.\\ \\ | ||
| ==== Exercise #5 - Download and Putty ==== | ==== Exercise #5 - Download and Putty ==== | ||
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| Then, using switches and buttons to transmit characters to Putty and see if they appear on the screen. | Then, using switches and buttons to transmit characters to Putty and see if they appear on the screen. | ||
| + | |||
| + | ===== Final Pass Off ===== | ||
| + | |||
| + | To pass off this laboratory, demonstrate to the TA the following: | ||
| + | * Pass-offs for Exercises 1, 2, and 3 | ||
| + | * Your working top-level uart transmitter/receiver circuit | ||
| + | |||
| + | <color red>How many hours did you work on the lab?</color> | ||
| + | |||
| + | <color red>Please provide any suggestions for improving this lab in the future.</color> | ||
| ===== Personal Exploration ===== | ===== Personal Exploration ===== | ||
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| <color red>Describe your personal exploration activities</color> | <color red>Describe your personal exploration activities</color> | ||
| - | ===== Pass Off ===== | ||
| - | |||
| - | To pass off this laboratory, demonstrate to the TA the following: | ||
| - | * Your testbench passing with 0 errors | ||
| - | * Your working top-level uart transmitter/receiver circuit | ||
| - | |||
| - | |||
| - | <color red>How many hours did you work on the lab?</color> | ||
| - | |||
| - | <color red>Please provide any suggestions for improving this lab in the future.</color> | ||
| Line 255: | Line 266: | ||
| characters). | characters). | ||
| */ | */ | ||
| - | |||
