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labs:structural_verilog [2020/04/20 14:35] nelson |
labs:structural_verilog [2020/04/20 14:35] (current) nelson [Exercise #2: Implement Logic Functions in Structural SystemVerilog] |
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| Although it is difficult to find logic errors in the schematic view, it is easy to see problems such as missing connections between the gates, inputs, and outputs. Look for unconnected top-level ports or missing connections in your gates (missing connections are annotated with **n/c** on the schematic). | Although it is difficult to find logic errors in the schematic view, it is easy to see problems such as missing connections between the gates, inputs, and outputs. Look for unconnected top-level ports or missing connections in your gates (missing connections are annotated with **n/c** on the schematic). | ||
| - | **Exercise 2 Pass-off:** Review your code with a TA. And, a TA your circuit schematic (the schematic under "RTL Analysis"). Be able to explain what each of the components are and how Vivado has implemented your four functions.\\ \\ | + | **Exercise 2 Pass-off:** Review your code with a TA as well as your circuit schematic (the schematic under "RTL Analysis"). Be able to explain what each of the components are and how Vivado has implemented your four functions.\\ \\ |
| /* I think it would be useful to add a question that asks them to compare the schematic to their logic functions. In particular, it would be useful to have them create a logic equation for each output based on the gates that were chosen. Then, have them prove that the logic equations are the same. This may be difficult to do in learning suite but it is an interesting exercise for them to complete. | /* I think it would be useful to add a question that asks them to compare the schematic to their logic functions. In particular, it would be useful to have them create a logic equation for each output based on the gates that were chosen. Then, have them prove that the logic equations are the same. This may be difficult to do in learning suite but it is an interesting exercise for them to complete. | ||
